Target device: AGX Xavier Devkit 16G.
Software: L4t r32.7.3, SPE-FW r32.6.1
Test procedure:
(1) I enable IVC, CAN, SPI official demo based on the Official Tutorial, And IVC, CAN, SPI(only PIO mode) work fine.
(2) Modified code in l4t-rt/rt-aux-cpu-demo/app/spi-app.c:
#define SPI_TEST_RETRIES 5000
#define SPI_TEST_DELAY 2000
char data_to_send[512]; // my add
char data_to_read[512]; // my add
extern int en_spi_flag; //set a flag to enable spi by the IVC
static portTASK_FUNCTION(spi_test_task, pvParameters)
{
// const uint8_t data_to_send[] = {0x01, 0x23, 0x45,0x67, 0x89, 0xab, 0xcd, 0xef};
// uint8_t data_to_read[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
data_to_send[0]=0x01; // my add
data_to_send[1]=0x23; // my add
data_to_send[2]=0x45; // my add
int ret, count;
struct tegra_spi_xfer xfer = {
.flags = BIT(TEGRA_SPI_XFER_FIRST_MSG) |
BIT(TEGRA_SPI_XFER_LAST_MSG),
.tx_buf = data_to_send,
.rx_buf = data_to_read,
.len = ARRAY_SIZE(data_to_read),
.chip_select = 0,
.tx_nbits = TEGRA_SPI_NBITS_SINGLE,
.rx_nbits = TEGRA_SPI_NBITS_SINGLE,
.bits_per_word = 8,
.mode = TEGRA_SPI_MODE_1 | TEGRA_SPI_LSBYTE_FIRST,
};
(void)pvParameters; /* unused */
for (count = 0; count < SPI_TEST_RETRIES; count++) {
memset(data_to_read,0,ARRAY_SIZE(data_to_read));
if (en_spi_flag > 3) // my add
{
ret = tegra_spi_transfer(&SPI_TEST_CONTROLLER, &xfer);
if (ret)
printf("SPI TX/RX failed\r\n");
else {
if (!memcmp(data_to_read, data_to_send,
ARRAY_SIZE(data_to_read)))
printf("SPI test successful\r\n");
else
printf("Received incorrect data\r\n");
}
}
vTaskDelay(SPI_TEST_DELAY);
}
vTaskDelete(NULL);
}
(3) Modified code in l4t-rt/rt-aux-cpu-demo/app/ivc-echo-task.c:
int en_spi_flag; //my add
static void ivc_echo_task_process_ivc_messages(struct ivc_echo_task_state *state)
{
int ret;
const char *rx_msg;
bool non_contig_available;
int count, i;
en_spi_flag++; // my add
for (;;)
{
xSemaphoreTake(state->ivc_sem, portMAX_DELAY);
count = tegra_ivc_rx_get_contiguous_read_available(
state->id->ivc_ch, &rx_msg, &non_contig_available);
xSemaphoreGive(state->ivc_sem);
printf("IVC read count: %d\r\n", count);
~~~~~~~~~~~~~~~~~~~~~~~~~
}
In addition, I have not made any changes to the code
(4) I compile and flash the spe-fw partition by running:
make CROSS_COMPILE=arm-none-eabi- bin_t19x
sudo ./flash.sh -r -k spe-fw jetson-xavier mmcblk0p1
(5) After flash and reboot successfully, I run the following command three times (en_spi_flag > 3) to enable SPI:
sudo bash -c "echo 01234568 > /sys/devices/aon_echo/data_channel"
(6) The error logs occur:
--------------------------------------------------------------------------------
Exception: Data abort
DFAR: 0x00000000, DFSR: 0x00001c06
PC: 0x0c491900
LR: 0x0c48f8ac, SP: 0x0c4a5588, PSR: 0x6000001f
R0: 0x00000000, R1: 0x00000001, R2: 0x00000200
R3: 0x00000000, R4: 0x00000000, R5: 0x00000000
R6: 0x00000000, R7: 0x00000000, R8: 0x00000000
R9: 0x00000000, R10: 0x00000000, R11: 0x0c000001
R12: 0x0c485610
--------------------------------------------------------------------------------
(7) I run the addr2line command:
arm-none-eabi-addr2line -e $SPE_TOP_PATH/rt-aux-cpu-demo/out/t19x/spe.elf -a -f 0x0c491900 0x0c48f8ac
0x0c491900
tegra_spi_transfer
/home/***/nvidia/r3273agx/spe/l4t-rt/freertos-common/code-common/spi-tegra.c:1127
0x0c48f8ac
tegra_spi_copy_spi_rxbuf_to_client_rxbuf
/home/***/nvidia/r3273agx/spe/l4t-rt/freertos-common/code-common/spi-tegra.c:374
Finally, my .elf file is as follow:
spe.elf (33.1 MB)
I am looking forward to your test results. @jachen