How to set Baud Rate

In chapter of Xavier_TRM_DP09253002_v1.4p document, it is mentioned that we need configure CLK_RST_CONTROLLER_CLK_SOURCE_UART*_0 register to set UART baud rate.

Clock Divisor Options

UART dll/dlm registers, clk divisor as in the clock registers.

To achieve the required baud rate for a given UART controller, the

CLK_RST_CONTROLLER_CLK_SOURCE_UART*_0 register should be programmed. The source of the clock

can be chosen by programming [31:29] of this register and divisor by programming [15:0].

To achieve a divisor value of ‘X’, the register should be configured with value N=((X-1)*2).

Programming bit 24 determines if the programmed [15:0] divisor should be used or the DLM/DLL value from

UART. Only one of them can be used at a time.

As our understanding, such reigster belongs to CAR block. According to chapter 8.2 description, it seems we cannot configure such register.

For Xavier clocks and resets are controlled by NVIDIA provided firmware running on BPMP. The

hardware interface to the clock and reset controls is not documented, and the software documentation

should be consulted for details of how these functions are controlled.

I have tried to modify the

	uartc: serial@c280000 {
		compatible = "nvidia,tegra186-hsuart";
		iommus = <&smmu TEGRA_SID_GPCDMA_0>;
		reg = <0x0 0xc280000 0x0 0x10000>;
		reg-shift = <2>;
		interrupts = <0 TEGRA194_IRQ_UARTC 0x04>;
		nvidia,memory-clients = <14>;
		dmas = <&gpcdma 3>, <&gpcdma 3>;
		dma-names = "rx", "tx";
		clocks = <&bpmp_clks TEGRA194_CLK_UARTC>,
			<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
		clock-names = "serial", "parent";
		resets = <&bpmp_resets TEGRA194_RESET_UARTC>;
		reset-names = "serial";
		status = "okay";
		nvidia,tolerance-low-range = <0>;
		nvidia,tolerance-high-range = <4>;
		nvidia,adjust-baud-rates = <9600 9600 100>;

and replaced the dtb, but it still not work.

How can I change the baud rate to 9600?

hello YHuang0915,

please refer to Topic 110229 for IOCTL commands to configure baud-rate.