In chapter 10.4.1.4.1 of Xavier_TRM_DP09253002_v1.4p document, it is mentioned that we need configure CLK_RST_CONTROLLER_CLK_SOURCE_UART*_0 register to set UART baud rate.
Clock Divisor Options
UART dll/dlm registers, clk divisor as in the clock registers.
To achieve the required baud rate for a given UART controller, the
CLK_RST_CONTROLLER_CLK_SOURCE_UART*_0 register should be programmed. The source of the clock
can be chosen by programming [31:29] of this register and divisor by programming [15:0].
To achieve a divisor value of ‘X’, the register should be configured with value N=((X-1)*2).
Programming bit 24 determines if the programmed [15:0] divisor should be used or the DLM/DLL value from
UART. Only one of them can be used at a time.
As our understanding, such reigster belongs to CAR block. According to chapter 8.2 description, it seems we cannot configure such register.
For Xavier clocks and resets are controlled by NVIDIA provided firmware running on BPMP. The
hardware interface to the clock and reset controls is not documented, and the software documentation
should be consulted for details of how these functions are controlled.