How to set cil_settletime for AGX Orin developer kit?

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
1

We develop based on the AGX Orin developer kit. Currently, a sensor is connected, the data format is RAW8, the resolution is 4096*512, the frame rate is 10fps, the num_lanes is 4, the mclk_khz is 25000, the serdes_pix_clk_hz is 400000000, and the cil_settletime is 0. LP sequence error appeared. The trace log is as follows:

kworker/3:2-154     [003] ....    80.990073: rtcpu_nvcsi_intr: tstamp:3348266283 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000088
kworker/3:2-154     [003] ....    80.990075: rtcpu_nvcsi_intr: tstamp:3348266283 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000088
kworker/3:2-154     [003] ....    80.990077: rtcpu_vinotify_event: tstamp:3348346438 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:107136650144 data:0x379d580010000000
kworker/3:2-154     [003] ....    80.990077: rtcpu_vinotify_event: tstamp:3348346569 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:107136656608 data:0x0000000031000001
kworker/3:2-154     [003] ....    80.990077: rtcpu_vinotify_event: tstamp:3348346721 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:107136697024 data:0x379d550010000000
kworker/3:2-154     [003] ....    80.990078: rtcpu_vinotify_event: tstamp:3348346849 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:107136703584 data:0x0000000031000002
kworker/3:2-154     [003] ....    81.214230: rtcpu_nvcsi_intr: tstamp:3354820809 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214232: rtcpu_nvcsi_intr: tstamp:3354822199 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214232: rtcpu_nvcsi_intr: tstamp:3354822871 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214233: rtcpu_nvcsi_intr: tstamp:3354823251 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214233: rtcpu_nvcsi_intr: tstamp:3354823606 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214234: rtcpu_nvcsi_intr: tstamp:3354824275 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214235: rtcpu_nvcsi_intr: tstamp:3354824655 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214235: rtcpu_nvcsi_intr: tstamp:3354825014 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214236: rtcpu_nvcsi_intr: tstamp:3354825683 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214236: rtcpu_nvcsi_intr: tstamp:3354826063 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214237: rtcpu_nvcsi_intr: tstamp:3354826420 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214238: rtcpu_nvcsi_intr: tstamp:3354827089 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080
kworker/3:2-154     [003] ....    81.214238: rtcpu_nvcsi_intr: tstamp:3354827470 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080

For the value of cil_settletime, the guide gives the following calculation method:

•For NVIDIA® Jetson™ Nano devices and Jetson TX1:
image
Where one lp clock period is 1/(102 MHz).
•For NVIDIA® Jetson AGX Xavier™ series and Jetson TX2 series:
image
Where one lp clock period is 1/(204 MHz).

So how to set the value of cil_settletime on the AGX Orin developer kit?

3

hello wq.zhou,

there shows PHY interrupts, which indicate LP sequence error has detected on data lane.
normally, it should follow by LP11->LP01->LP00->LP11 sequence. please also probe the hardware signaling to review it.

while cil_settletime=0, it’s auto calculate the settings, you may also examine the signal for moving from LP to HS. the settle time determine how many cscil clock cycles to wait after LP00.

5

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