How to set the frequency of CAM0_MCLK?

Robotics & Edge Computing Jetson & Embedded Systems Jetson Xavier NX
1

Hi,

We are trying to set a proper clock frequency for CAM0_MCLK.

cam0_mclk
cam0_mclk1011×237 30.4 KB

We transfer the tegra194-a02-bpmp-p3668-a00.dtb under ~/nvidia/nvidia_sdk/JetPack_4.5_Linux_JETSON_XAVIER_NX/Linux_for_Tegra/bootloader/t186ref/ back to dts. The following “freq” fields should be able to change the clock frequency.

		clock@extperiph1 {
			clk-id = <0x24>;

			rail@vdd_soc {
				rail-id = <0x2>;

				bin@1492 {
					bin-bottom = <0x5d4>;

					opp@0 {
						cvb-coeffs = <0x3f224745 0x0 0x0>;
						freq = <0x0 0x235f65d>;
					};
				};

				bin@1599 {
					bin-bottom = <0x63f>;

					opp@1 {
						cvb-coeffs = <0x3f224745 0x0 0x0>;
						freq = <0x0 0x235f65d>;
					};
				};

				bin@1707 {
					bin-bottom = <0x6ab>;

					opp@2 {
						cvb-coeffs = <0x3f224745 0x0 0x0>;
						freq = <0x0 0x235f65d>;
					};
				};
			};
		};

Could you help us understand why there are 3 freq fields in different bin scopes of clock@extperiph1? What are those meanings of bin@1492, bin@1599 and bin@1707? We discover some SOMs use bin@1599 while others use bin@1707.

3

Have a check this document to define the mclk in device tree like in sensor scope and sensor driver will set it to the request freq when open the driver.

https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/camera_sensor_prog.html#wwpID0E0Q50HA

4

Hi Shane,

Thank you for the document.

Because our driver may not follow the structure of NVIDIA Tegra camera system, we would like to know more about the BPMP clocks which should be the sources of all clocks and could be directly used by any driver.

Could you help provide the followings?

  1. any document describing the BPMP clocks
  2. the original device tree source file of tegra194-a02-bpmp-p3668-a00.dtb
6

the bins are basically various buckets of chips from wafer which has different characteristics. And DVFS is applied based on the chip SKU.
You should not be changing clocks from bpmp dts.

please go through this
https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/clocks.html#wwconnect_header

7

Hi Bibek,

Thank you for your help. It is much clearer now.

You mentioned about various buckets of chips from wafer which has different characteristics. Could we tell which bin is used on an SOM? For example, we have two NX modules which are both labeled as 180-I3668-DAAA-A02 and both have 900-83668-0000-000 codes. However, they use different bins in the BPMP setting. This is a little confusing for us because these two NX modules look the same from their appearances.

8

what freq you want to set to and what is the present value?

9

Hi Bibek,

We hope to permanently change /sys/kernel/debug/bpmp/debug/clk/extperiph1/rate to 27000000. So we make the following change:

				bin@1599 {
					bin-bottom = <0x5d4>;

					opp@0 {
						cvb-coeffs = <0x3f224745 0x0 0x0>;
-						freq = <0x0 0x235f65d>;
+						freq = <0x0 0x19bfcc0>;
					};
				};

After we change the freq to <0x0 0x19bfcc0>, the frequency becomes 27200000 but not 27000000.

What we really concern is how bin@1492, bin@1599 or bin@1707 is chosen to be used by an SOM. If an SOM is beyond 1492, 1599 and 1707, we will have an invalid clock. To avoid this case, we may consider to use an external clock.

10

bin is selected based on SoC speedo value. These values in the dt are threshold speedo values. All possible speedo values should be covered here. If the actual speedo is below minimum supported, then minimum speedo related settings is applied. bin-bottom is the minimum speedo value for which the coefficients for deriving Vmin is selected.
The difference in frequency should be because of the clock limitation.
With the 3 possible parents, 27.2 Mhz is the nearest freq that can be set.