How to use IMX318 on TX2

We want to use cphy in tx2, then find the imx318 cphy support in the device tree, so we want to know how to connect imx318 on tx2

hello 1290914897,

please access Tegra X2 (Parker Series SoC) Technical Reference Manual through Jetson Download Center,
you should check [CHAPTER 28: MIPI CAMERA SERIAL INTERFACE (CSI)] and refer to [28.4 Functionality] for the brick diagram.
BTW,
you may also check Sensor Software Driver Programming Guide for the device tree properties settings.
thanks

We connect the cphy module to receive raw10 data on another board, but we can’t receive data on tx2. The following is the 1trios case. 2/3trios shows no data on the mipi line:

kworker/5:2-8322 [005] … 4315.538790: rtos_queue_send_failed: tstamp:135980539632 queue:0x0b4a5e08
kworker/5:2-8322 [005] … 4315.594681: rtcpu_vinotify_event: tstamp:135982932193 tag:CSIMUX_FRAME channel:0x00 frame:151 vi_tstamp:135982931480 data:0x000000a0
kworker/5:2-8322 [005] … 4315.594684: rtcpu_vinotify_event: tstamp:135982932333 tag:CHANSEL_SHORT_FRAME channel:0x01 frame:151 vi_tstamp:135982931481 data:0x00000001
kworker/5:2-8322 [005] … 4315.594684: rtcpu_vinotify_event: tstamp:135982932468 tag:ATOMP_FE channel:0x00 frame:151 vi_tstamp:135982931482 data:0x00000001
kworker/5:2-8322 [005] … 4315.706704: rtos_queue_peek_from_isr_failed: tstamp:135985041115 queue:0x0b4b2ed8
kworker/5:2-8322 [005] … 4315.706709: rtcpu_vinotify_event: tstamp:135985106171 tag:CSIMUX_FRAME channel:0x00 frame:152 vi_tstamp:135985105803 data:0x000000a0

hello 1290914897,

in C-Phy mode, 1 trio = 3 pins, you should connect sensor to trio0/1/2 of the brick.
since there’s CHANSEL_SHORT_FRAME failure, you might adjust active_h settings in device tree to solve the issue.
thanks

We are sure that the image size is set correctly in the device tree, but we still can’t receive any data. Here’s how we connect to the IMX318:
csi_IO0P_A->A0
csi_IO0N_A->B0
csi_IOCLKP_A->C0
Csi_IOCLKN_A->A1
Csi_IO1P_A->C1
Csi_IO1N_A->B1
Csi_IO0P_B->A2
Csi_IO0N_B->B2
Csi_IOCLKP_B->C2
Is it right?

hello 1290914897,

these connections seems correct.
is it possible to probe the MIPI signaling to check the hardware and also power settings?
thanks

Hi 1290914897

Have you tried our suggestions to probe the MIPI signaling to check the hardware and also power settings?
Any result can be shared?

Now, we can receive the raw data from imx318 by using the 1trios parameter, but the 2/3tiros parameters still can’t receive any data, the device tree settings and the imx318 parameters are correct. Here is the connection for the second trios:
Csi_IOCLKN_A->A1
Csi_IO1P_A->C1
Csi_IO1N_A->B1
Is it right?

hello 1290914897,

according to the TegraX2 TRM diagram (Figure 205: NVCSI SCIL and Brick Interface for HS Path)
the lane swizzling unit comes after this block and it is the identity mapping, (ab/bc/ca).
for example,

trio_1

csi_ab_pad_cphy_dout1_rxab_a – 1A
csi_ab_pad_cphy_dout1_rxbc_a – 1B
csi_ab_pad_cphy_dout1_rxca_a – 1C

hello JerryChang,

We found that the CPHY connection was defined in the AGX’s instruction manual(Jetson_AGX_Xavier_Developer_Kit_Carrier_Board_Specification).
Can we refer to the hardware connection in AGX?

hello 1290914897,

sorry, just got the confirmation that there’s no C-PHY support on TX2.

Hi JerryChang,
We are confused about this, by using the parameters of 1trios, we can receive raw data on the TX2 board. Does it mean that we must pass AGX to receive CPHY data?

hello 1290914897,

per TX2, we only share reference design in TX2 OEM Design Guide, and it’s only for D-PHY info in module datasheet.
please also refer to similar discussion thread, Topic 1065560 for more details.
thanks