How to use PCIE C4 root port?

The AGX carrier card is designed by us. We connected the PCIE (C4) controller to the PCIE to USB device. The PCIE data width is X1 (UPHY_TX8_P/N,UPHY_RX8_P/N), and the mode is ROOT, but the following error occurred. How should it be modified.

Test that the PEX_L4_RST_N pin is always low,and AGX has no clock output,and CLK_REQ_N is always low.

The following picture shows the location of our modification (see the attachment for the entire file)

tegra194-p2888-0000-a00.dtsi (6.1 KB)
The printing information is as follows:

dmesg.txt (69.4 KB)

please refer to

Our board actually uses the X1 mode of PCIE C4, do we just add

phys = <&p2u_8>;
phy-names = “pcie-p2u-0”;

Our kernel version is Kernel-4.9.