How to use PCIE C4 root port?

[Kimber]

The AGX carrier card is designed by us. We connected the PCIE (C4) controller to the PCIE to USB device. The PCIE data width is X1 (UPHY_TX8_P/N，UPHY_RX8_P/N), and the mode is ROOT， but the following error occurred. How should it be modified.

Test that the PEX_L4_RST_N pin is always low，and AGX has no clock output，and CLK_REQ_N is always low.

The following picture shows the location of our modification (see the attachment for the entire file)

tegra194-p2888-0000-a00.dtsi (6.1 KB)
The printing information is as follows：

dmesg.txt (69.4 KB)

[WayneWWW]

please refer to

PCIe C4 not working

What is the release you are using? Is it Kernel-4.9 or Kernel-5.10? If you are using kernel-4.9, please add the following phys = <&p2u_8>, <&p2u_9>; phy-names = "pcie-p2u-0", "pcie-p2u-1"; If you are using Kernel-5.10, add the following instead phys = <&p2u_hsio_8>, <&p2u_hsio_9>; phy-names = "p2u-0", "p2u-1"; Please also share the log and describe the new issue if it doesn’t work a…

[Kimber]

@PCIe C4 not working

phys = <&p2u_8>,
                      <&p2u_9>;

Our board actually uses the X1 mode of PCIE C4, do we just add

phys = <&p2u_8>;
phy-names = “pcie-p2u-0”;

[Kimber]

Our kernel version is Kernel-4.9.