# \[HW\] ORIN CONFIG 2 BOARD

**URL:** <https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114>\
**Category:** Jetson AGX Orin\
**Tags:** pcie, board-design\
**Created:** [April 12, 2025, 3:17am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114 "2025-04-12T03:17:50Z")\
**Posts on this page:** 18\
**Page:** 1

<div class="post-metadata">

**Author:** ![jackbuffett](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jackbuffett](https://forums.developer.nvidia.com/u/jackbuffett)\
**Post date:** [April 12, 2025, 3:17am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/1 "2025-04-12T03:17:50Z")

</div>

Please provide the following info (tick the boxes after creating this topic):  
**Target Operating System**  
[●] Linux  
**Hardware Platform**  
[●] other

**Issue Description**  
\<Please provide details about your query/application pipeline/usecase/pictures here \>  
We’ve built the board. We’ve almost finished changing the PMIC, the power chip.  
I am currently bringing up the board and the power sequence is the same as below.

 ![image](https://global.discourse-cdn.com/nvidia/original/4X/0/e/5/0e508cf4df900864d1497babe47284ead35bca65.jpeg)  
The issue is that when 12V power is applied, a current of about 1.2A to 800mA appears.  
But it doesn’t boot and UART3 USB doesn’t show up either.  
We designed the board as Config #2.  
 ![image](https://global.discourse-cdn.com/nvidia/original/4X/3/2/6/326777f513e0b332f40596d648ac6f43928e1a39.png)  
If I apply Config#1 to the ORIN module, won’t the UART3 message come out?  
Most of the checks are complete. I couldn’t attach it because there was no message from USB Debug. Is there anything else I should check?  
Thanks.

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<div class="post-metadata">

**Author:** ![SivaRamaKrishnaNV](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/sivaramakrishnanv/32/14043_2.png) [@SivaRamaKrishnaNV](https://forums.developer.nvidia.com/u/SivaRamaKrishnaNV)\
**Post date:** [April 12, 2025, 3:51am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/2 "2025-04-12T03:51:20Z")

</div>

Dear @jackbuffett ,  
Are you using DRIVE AGX orin or Jetson AGX orin?

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<div class="post-metadata">

**Author:** ![jackbuffett](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jackbuffett](https://forums.developer.nvidia.com/u/jackbuffett)\
**Post date:** [April 12, 2025, 4:20am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/3 "2025-04-12T04:20:33Z")

</div>

Sorry, This is Jetson AGX orin.

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<div class="post-metadata">

**Author:** ![WayneWWW](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/waynewww/32/14043_2.png) [@WayneWWW](https://forums.developer.nvidia.com/u/WayneWWW)\
**Post date:** [April 12, 2025, 9:42am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/4 "2025-04-12T09:42:19Z")

</div>

USB won’t give out any log during boot up stage. Why do you keep mentioning USB debug?

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<div class="post-metadata">

**Author:** ![jackbuffett](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jackbuffett](https://forums.developer.nvidia.com/u/jackbuffett)\
**Post date:** [April 13, 2025, 9:55pm UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/5 "2025-04-13T21:55:09Z")

</div>

This is because I had an experience where a USB LOG appeared after booting when developing XAVIER previously.  
Internally we are changing CONFIG#2.  
I would like to know before changing it. I would like to know if the CONFIG configuration may not boot if the hardware is different.

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<div class="post-metadata">

**Author:** ![WayneWWW](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/waynewww/32/14043_2.png) [@WayneWWW](https://forums.developer.nvidia.com/u/WayneWWW)\
**Post date:** [April 14, 2025, 3:34am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/7 "2025-04-14T03:34:44Z")

</div>

Changing UPHY configuration won’t make the log disappeared. The UART side should always give some print.

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<div class="post-metadata">

**Author:** ![jackbuffett](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jackbuffett](https://forums.developer.nvidia.com/u/jackbuffett)\
**Post date:** [April 15, 2025, 6:31am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/8 "2025-04-15T06:31:05Z")

</div>

Thanks for your guide.  
I have some additional questions.

1. Can I NC the pin below?  
 ![image](https://global.discourse-cdn.com/nvidia/original/4X/8/8/1/88134c31d75ae2a87a6b276f3306bf1a38d2a4e3.png)
2. Do I need data if I use ATSAMD21G16B-AU\_P3737? I asked because I heard in some forum that it is not needed.  
If I need data, this is what I think is causing it.

---

<div class="post-metadata">

**Author:** ![jackbuffett](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jackbuffett](https://forums.developer.nvidia.com/u/jackbuffett)\
**Post date:** [April 15, 2025, 7:29am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/9 "2025-04-15T07:29:39Z")

</div>

I have completed verification with the Demo Board.  
JTAG seems to be fine.  
When I apply the demo board chip, the USB is recognized. So it seems that data is needed.  
But it still won’t boot. Are there any more pins I need to check?

---

<div class="post-metadata">

**Author:** ![WayneWWW](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/waynewww/32/14043_2.png) [@WayneWWW](https://forums.developer.nvidia.com/u/WayneWWW)\
**Post date:** [April 15, 2025, 7:31am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/10 "2025-04-15T07:31:19Z")

</div>

Just to clarify. So is your UART giving out any log now or not?

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<div class="post-metadata">

**Author:** ![jackbuffett](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jackbuffett](https://forums.developer.nvidia.com/u/jackbuffett)\
**Post date:** [April 15, 2025, 8:38am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/11 "2025-04-15T08:38:54Z")

</div>

We have demo boards and Som modules.  
When I applied config#2 to the SOM module and connected it to the demo board, it did not work.  
When we applied config#2 to the Som module and connected it to our production board, the log file below was output.

> **Summary**
>
> ▒▒  
> [0000.067] I\> MB1 (version: 1.4.0.2-t234-54845784-08a4de08)  
> [0000.072] I\> t234-A01-0-Silicon (0x12347) Prod  
> [0000.076] I\> Boot-mode : Coldboot  
> [0000.079] I\> Entry timestamp: 0x00000000  
> [0000.083] I\> last\_boot\_error: 0x0  
> [0000.086] I\> BR-BCT: preprod\_dev\_sign: 0  
> [0000.090] I\> rst\_source: 0x0, rst\_level: 0x0  
> [0000.094] I\> Task: SE error check  
> [0000.097] I\> Task: Bootchain select WAR set  
> [0000.101] I\> Task: Enable SLCG  
> [0000.104] I\> Task: CRC check  
> [0000.107] I\> Skip FUSE records CRC check as records\_integrity fuse is not burned  
> [0000.114] I\> Task: Initialize MB2 params  
> [0000.118] I\> MB2-params @ 0x40060000  
> [0000.122] I\> Task: Crypto init  
> [0000.125] I\> Task: Perform MB1 KAT tests  
> [0000.129] I\> Task: NVRNG health check  
> [0000.132] I\> NVRNG: Health check success  
> [0000.136] I\> Task: MSS Bandwidth limiter settings for iGPU clients  
> [0000.142] I\> Task: Enabling and initialization of Bandwidth limiter  
> [0000.148] I\> No request to configure MBWT settings for any PC!  
> [0000.154] I\> Task: Secure debug controls  
> [0000.158] I\> Task: strap war set  
> [0000.161] I\> Task: Initialize SOC Therm  
> [0000.164] I\> Task: Program NV master stream id  
> [0000.169] I\> Task: Verify boot mode  
> [0000.174] I\> Task: Alias fuses  
> [0000.178] W\> FUSE\_ALIAS: Fuse alias on production fused part is not supported.  
> [0000.185] I\> Task: Print SKU type  
> [0000.188] I\> FUSE\_OPT\_CCPLEX\_CLUSTER\_DISABLE = 0x000001c0  
> [0000.194] I\> FUSE\_OPT\_GPC\_DISABLE = 0x00000000  
> [0000.198] I\> FUSE\_OPT\_TPC\_DISABLE = 0x00000020  
> [0000.202] I\> FUSE\_OPT\_DLA\_DISABLE = 0x00000000  
> [0000.206] I\> FUSE\_OPT\_PVA\_DISABLE = 0x00000000  
> [0000.211] I\> FUSE\_OPT\_NVENC\_DISABLE = 0x00000000  
> [0000.215] I\> FUSE\_OPT\_NVDEC\_DISABLE = 0x00000000  
> [0000.220] I\> FUSE\_OPT\_FSI\_DISABLE = 0x00000000  
> [0000.224] I\> FUSE\_OPT\_EMC\_DISABLE = 0x00000000  
> [0000.228] I\> FUSE\_BOOTROM\_PATCH\_VERSION = 0x7  
> [0000.232] I\> FUSE\_PSCROM\_PATCH\_VERSION = 0x7  
> [0000.236] I\> FUSE\_OPT\_ADC\_CAL\_FUSE\_REV = 0x2  
> [0000.240] I\> FUSE\_SKU\_INFO\_0 = 0xd2  
> [0000.244] I\> FUSE\_OPT\_SAMPLE\_TYPE\_0 = 0x3 PS  
> [0000.248] I\> FUSE\_PACKAGE\_INFO\_0 = 0x2  
> [0000.252] I\> SKU: Prod  
> [0000.254] I\> Task: Boost clocks  
> [0000.257] I\> Initializing NAFLL for BPMP\_CPU\_NIC.  
> [0000.262] I\> BPMP NAFLL: fll\_lock = 1, dvco\_min\_reached = 0  
> [0000.267] I\> BPMP NAFLL lock success.  
> [0000.271] I\> BPMP\_CPU\_NIC : src = 42, divisor = 0  
> [0000.275] I\> Initializing PLLC2 for AXI\_CBB.  
> [0000.280] I\> AXI\_CBB : src = 35, divisor = 0  
> [0000.284] I\> Task: Voltage monitor  
> [0000.287] I\> VMON: Vmon re-calibration and fine tuning done  
> [0000.292] I\> Task: UPHY init  
> [0000.297] I\> HSIO UPHY init done  
> [0000.300] W\> Skipping GBE UPHY config  
> [0000.304] I\> Task: Boot device init  
> [0000.307] I\> Boot\_device: QSPI\_FLASH instance: 0  
> [0000.312] I\> Qspi clock source : pllc\_out0  
> [0000.316] I\> QSPI Flash: Macronix 64MB  
> [0000.319] I\> QSPI-0l initialized successfully  
> [0000.324] I\> Task: TSC init  
> [0000.327] I\> Task: Load membct  
> [0000.329] I\> RAM\_CODE 0x4000401  
> [0000.332] I\> Loading MEMBCT  
> [0000.335] I\> Slot: 0  
> [0000.337] I\> Binary[0] block-3840 (partition size: 0x40000)  
> [0000.343] I\> Binary name: MEM-BCT-0  
> [0000.346] I\> Size of crypto header is 8192  
> [0000.350] I\> Size of crypto header is 8192  
> [0000.354] I\> strt\_pg\_num(3840) num\_of\_pgs(16) read\_buf(0x40050000)  
> [0000.360] I\> BCH of MEM-BCT-0 read from storage  
> [0000.364] I\> BCH address is : 0x40050000  
> [0000.368] I\> MEM-BCT-0 header integrity check is success  
> [0000.374] I\> Binary magic in BCH component 0 is MEM0  
> [0000.378] I\> component binary type is 0  
> [0000.382] I\> strt\_pg\_num(3856) num\_of\_pgs(115) read\_buf(0x40040000)  
> [0000.389] I\> MEM-BCT-0 binary is read from storage  
> [0000.394] I\> MEM-BCT-0 binary integrity check is success  
> [0000.399] I\> Binary MEM-BCT-0 loaded successfully at 0x40040000 (0xe580)  
> [0000.405] I\> RAM\_CODE 0x4000401  
> [0000.411] I\> RAM\_CODE 0x4000401  
> [0000.415] I\> Task: Load Page retirement list  
> [0000.419] I\> Task: SDRAM params override  
> [0000.422] I\> Task: Save mem-bct info  
> [0000.426] I\> Task: Carveout allocate  
> [0000.429] I\> RCM blob carveout will not be allocated  
> [0000.434] I\> Update CCPLEX IST carveout from MB1-BCT  
> [0000.439] I\> ECC region[0]: Start:0x0, End:0x0  
> [0000.443] I\> ECC region[1]: Start:0x0, End:0x0  
> [0000.448] I\> ECC region[2]: Start:0x0, End:0x0  
> [0000.452] I\> ECC region[3]: Start:0x0, End:0x0  
> [0000.456] I\> ECC region[4]: Start:0x0, End:0x0  
> [0000.460] I\> Non-ECC region[0]: Start:0x80000000, End:0x880000000  
> [0000.466] I\> Non-ECC region[1]: Start:0x0, End:0x0  
> [0000.471] I\> Non-ECC region[2]: Start:0x0, End:0x0  
> [0000.476] I\> Non-ECC region[3]: Start:0x0, End:0x0  
> [0000.480] I\> Non-ECC region[4]: Start:0x0, End:0x0  
> [0000.491] I\> allocated(CO:44) base:0x849800000 size:0x36800000 align: 0x100000  
> [0000.498] I\> allocated(CO:31) base:0x840000000 size:0x8000000 align: 0x8000000  
> [0000.505] I\> allocated(CO:43) base:0x83c000000 size:0x4000000 align: 0x200000  
> [0000.512] I\> allocated(CO:39) base:0x839e00000 size:0x2200000 align: 0x10000  
> [0000.519] I\> allocated(CO:20) base:0x836000000 size:0x2000000 align: 0x2000000  
> [0000.526] I\> allocated(CO:24) base:0x834000000 size:0x2000000 align: 0x2000000  
> [0000.533] I\> allocated(CO:28) base:0x832000000 size:0x2000000 align: 0x2000000  
> [0000.541] I\> allocated(CO:29) base:0x830000000 size:0x2000000 align: 0x2000000  
> [0000.548] I\> allocated(CO:22) base:0x848000000 size:0x1000000 align: 0x1000000  
> [0000.555] I\> allocated(CO:35) base:0x838e00000 size:0x1000000 align: 0x100000  
> [0000.562] I\> allocated(CO:41) base:0x82f000000 size:0x1000000 align: 0x100000  
> [0000.569] I\> allocated(CO:02) base:0x849000000 size:0x800000 align: 0x800000  
> [0000.576] I\> allocated(CO:03) base:0x838000000 size:0x800000 align: 0x800000  
> [0000.583] I\> allocated(CO:06) base:0x82e800000 size:0x800000 align: 0x800000  
> [0000.590] I\> allocated(CO:56) base:0x82e000000 size:0x800000 align: 0x200000  
> [0000.597] I\> allocated(CO:07) base:0x838800000 size:0x400000 align: 0x400000  
> [0000.604] I\> allocated(CO:33) base:0x82dc00000 size:0x400000 align: 0x200000  
> [0000.610] I\> allocated(CO:19) base:0x82d980000 size:0x280000 align: 0x10000  
> [0000.617] I\> allocated(CO:23) base:0x838c00000 size:0x200000 align: 0x200000  
> [0000.624] I\> allocated(CO:01) base:0x82d800000 size:0x100000 align: 0x100000  
> [0000.631] I\> allocated(CO:05) base:0x82d700000 size:0x100000 align: 0x100000  
> [0000.638] I\> allocated(CO:08) base:0x82d600000 size:0x100000 align: 0x100000  
> [0000.645] I\> allocated(CO:09) base:0x82d500000 size:0x100000 align: 0x100000  
> [0000.652] I\> allocated(CO:12) base:0x82d400000 size:0x100000 align: 0x100000  
> [0000.659] I\> allocated(CO:15) base:0x82d300000 size:0x100000 align: 0x100000  
> [0000.666] I\> allocated(CO:17) base:0x82d200000 size:0x100000 align: 0x100000  
> [0000.673] I\> allocated(CO:27) base:0x82d100000 size:0x100000 align: 0x100000  
> [0000.680] I\> allocated(CO:42) base:0x82d000000 size:0x100000 align: 0x100000  
> [0000.687] I\> allocated(CO:54) base:0x82d900000 size:0x80000 align: 0x80000  
> [0000.694] I\> allocated(CO:34) base:0x82cff0000 size:0x10000 align: 0x10000  
> [0000.700] I\> allocated(CO:72) base:0x82cdf0000 size:0x200000 align: 0x10000  
> [0000.707] I\> allocated(CO:47) base:0x82c800000 size:0x400000 align: 0x200000  
> [0000.714] I\> allocated(CO:50) base:0x82c600000 size:0x200000 align: 0x100000  
> [0000.721] I\> allocated(CO:52) base:0x82cdc0000 size:0x30000 align: 0x10000  
> [0000.728] I\> allocated(CO:48) base:0x82cda0000 size:0x20000 align: 0x10000  
> [0000.735] I\> allocated(CO:69) base:0x82cd80000 size:0x20000 align: 0x10000  
> [0000.741] I\> allocated(CO:49) base:0x82cd70000 size:0x10000 align: 0x10000  
> [0000.748] I\> NSDRAM base: 0x80000000, end: 0x82cdf0000, size: 0x7acdf0000  
> [0000.755] I\> Task: Thermal check  
> [0000.758] I\> Using min\_chip\_limit as min\_tmon\_limit  
> [0000.763] I\> Using max\_chip\_limit as max\_tmon\_limit  
> [0000.767] I\> BCT max\_tmon\_limit = 105  
> [0000.771] I\> BCT min\_tmon\_limit = -28  
> [0000.774] I\> BCT max\_tmon\_limit = 105  
> [0000.778] I\> BCT min\_tmon\_limit = -28  
> [0000.781] I\> SKU specific max\_chip\_limit = 105  
> [0000.786] I\> SKU specific min\_chip\_limit = -28  
> [0000.790] I\> BCT max\_chip\_limit = 105  
> [0000.793] I\> BCT min\_chip\_limit = -28  
> [0000.797] I\> enable\_soctherm\_polling = 0  
> [0000.801] I\> max temp read = 34  
> [0000.804] I\> min temp read = 33  
> [0000.807] I\> Enabling thermtrip  
> [0000.809] I\> Task: Update FSI SCR with thermal fuse data  
> [0000.815] I\> Task: Enable WDT 5th expiry  
> [0000.818] I\> Task: I2C register  
> [0000.821] I\> Task: Set I2C bus freq  
> [0000.825] I\> Task: Reset FSI  
> [0000.828] I\> Task: Pinmux init  
> [0000.831] I\> Task: Prod config init  
> [0000.834] I\> Task: Pad voltage init  
> [0000.838] I\> Task: Prod init  
> [0000.840] I\> Task: Program rst req config reg  
> [0000.845] I\> Task: Common rail init  
> [0000.848] I\> DONE: Thermal config  
> [0000.852] W\> DEVICE\_PROD: module = 13, instance = 4 not found in device prod.  
> [0000.860] I\> DONE: SOC rail config  
> [0000.864] W\> PMIC\_CONFIG: Rail: MEMIO rail config not found in MB1 BCT.  
> [0000.870] I\> DONE: MEMIO rail config  
> [0000.874] I\> DONE: GPU rail info  
> [0000.877] I\> DONE: CV rail info  
> [0000.880] I\> Task: Mem clock src  
> [0000.883] I\> Task: Misc. board config  
> [0000.887] I\> PMIC\_CONFIG: Platform config not found in MB1 BCT.  
> [0000.893] I\> Task: SDRAM init  
> [0000.895] I\> MemoryType: 4 MemBctRevision: 10  
> [0000.902] I\> MSS CAR: PLLM/HUB programming for MemoryType: 4 and MemBctRevision: 10  
> [0000.910] I\> MSS CAR: Init PLLM  
> [0000.913] I\> MSS CAR: Init PLLHUB  
> [0000.918] I\> Encryption: MTS: en, TX: en, VPR: en, GSC: en  
> [0000.929] I\> SDRAM initialized!  
> [0000.932] I\> SDRAM Size in Total 0x800000000  
> [0000.936] I\> Task: Dram Ecc scrub  
> [0000.939] I\> Task: DRAM alias check  
> [0000.956] I\> Task: Program NSDRAM carveout  
> [0000.960] I\> NSDRAM carveout encryption is enabled  
> [0000.964] I\> Program NSDRAM carveout  
> [0000.968] I\> Task: Register checker  
> [0000.971] I\> Task: Enable clock-mon  
> [0000.986] I\> FMON: Fmon re-programming done  
> [0000.990] I\> Task: Mapper init  
> [0000.993] I\> Task: SC7 Context Init  
> [0000.996] I\> Task: CCPLEX IST init  
> [0000.999] I\> Task: CPU WP0  
> [0001.002] I\> Loading MCE  
> [0001.005] I\> Slot: 0  
> [0001.007] I\> Binary[8] block-22784 (partition size: 0x80000)  
> [0001.012] I\> Binary name: MCE  
> [0001.015] I\> Size of crypto header is 8192  
> [0001.019] I\> Size of crypto header is 8192  
> [0001.023] I\> strt\_pg\_num(22784) num\_of\_pgs(16) read\_buf(0x4003e000)  
> [0001.029] I\> BCH of MCE read from storage  
> [0001.033] I\> BCH address is : 0x4003e000  
> [0001.037] I\> MCE header integrity check is success  
> [0001.042] I\> Binary magic in BCH component 0 is MTSM  
> [0001.046] I\> component binary type is 8  
> [0001.050] I\> Size of crypto header is 8192  
> [0001.054] I\> strt\_pg\_num(22800) num\_of\_pgs(350) read\_buf(0x40000000)  
> [0001.062] I\> MCE binary is read from storage  
> [0001.067] I\> MCE binary integrity check is success  
> [0001.071] I\> Binary MCE loaded successfully at 0x40000000 (0x2baf0)  
> [0001.078] I\> Size of crypto header is 8192  
> [0001.089] I\> Size of crypto header is 8192  
> [0001.093] I\> Sending WP0 mailbox command to PSC  
> [0001.102] I\> Task: XUSB Powergate  
> [0001.105] I\> Skipping powergate XUSB.  
> [0001.108] I\> Task: MB1 fixed firewalls  
> [0001.115] W\> Firewall readback mismatch  
> [0001.120] I\> Task: Load bpmp-fw  
> [0001.123] I\> Slot: 0  
> [0001.125] I\> Binary[15] block-9984 (partition size: 0x180000)  
> [0001.130] I\> Binary name: BPMP\_FW  
> [0001.133] I\> Size of crypto header is 8192  
> [0001.137] I\> Size of crypto header is 8192  
> [0001.141] I\> strt\_pg\_num(9984) num\_of\_pgs(16) read\_buf(0x807fe000)  
> [0001.147] I\> BCH of BPMP\_FW read from storage  
> [0001.152] I\> BCH address is : 0x807fe000  
> [0001.155] I\> BPMP\_FW header integrity check is success  
> [0001.160] I\> Binary magic in BCH component 0 is BPMF  
> [0001.165] I\> component binary type is 15  
> [0001.169] I\> Size of crypto header is 8192  
> [0001.173] I\> strt\_pg\_num(10000) num\_of\_pgs(1990) read\_buf(0x80000000)  
> [0001.191] I\> BPMP\_FW binary is read from storage  
> [0001.197] I\> BPMP\_FW binary integrity check is success  
> [0001.202] I\> Binary BPMP\_FW loaded successfully at 0x80000000 (0xf8bc0)  
> [0001.208] I\> Slot: 0  
> [0001.210] I\> Binary[16] block-13056 (partition size: 0x400000)  
> [0001.216] I\> Binary name: BPMP\_FW\_DTB  
> [0001.220] I\> Size of crypto header is 8192  
> [0001.223] I\> Size of crypto header is 8192  
> [0001.227] I\> strt\_pg\_num(13056) num\_of\_pgs(16) read\_buf(0x807fc000)  
> [0001.234] I\> BCH of BPMP\_FW\_DTB read from storage  
> [0001.238] I\> BCH address is : 0x807fc000  
> [0001.242] I\> BPMP\_FW\_DTB header integrity check is success  
> [0001.247] I\> Binary magic in BCH component 0 is BPMD  
> [0001.252] I\> component binary type is 16  
> [0001.256] I\> Size of crypto header is 8192  
> [0001.260] I\> strt\_pg\_num(13072) num\_of\_pgs(736) read\_buf(0x8079fff0)  
> [0001.270] I\> BPMP\_FW\_DTB binary is read from storage  
> [0001.276] I\> BPMP\_FW\_DTB binary integrity check is success  
> [0001.281] I\> Binary BPMP\_FW\_DTB loaded successfully at 0x8079fff0 (0x5bf00)  
> [0001.288] I\> Task: BPMP fw ast config  
> [0001.292] I\> Task: Load psc-fw  
> [0001.294] I\> Slot: 0  
> [0001.296] I\> Binary[17] block-21248 (partition size: 0xc0000)  
> [0001.302] I\> Binary name: PSC\_FW  
> [0001.305] I\> Size of crypto header is 8192  
> [0001.309] I\> Size of crypto header is 8192  
> [0001.313] I\> strt\_pg\_num(21248) num\_of\_pgs(16) read\_buf(0x80ffe000)  
> [0001.319] I\> BCH of PSC\_FW read from storage  
> [0001.323] I\> BCH address is : 0x80ffe000  
> [0001.327] I\> PSC\_FW header integrity check is success  
> [0001.332] I\> Binary magic in BCH component 0 is PFWP  
> [0001.337] I\> component binary type is 17  
> [0001.341] I\> Size of crypto header is 8192  
> [0001.345] I\> strt\_pg\_num(21264) num\_of\_pgs(591) read\_buf(0x80fb4200)  
> [0001.354] I\> PSC\_FW binary is read from storage  
> [0001.359] I\> PSC\_FW binary integrity check is success  
> [0001.364] I\> Binary PSC\_FW loaded successfully at 0x80fb4200 (0x49df0)  
> [0001.370] I\> Task: Load nvdec-fw  
> [0001.374] I\> Slot: 0  
> [0001.376] I\> Binary[7] block-6400 (partition size: 0x100000)  
> [0001.381] I\> Binary name: NVDEC  
> [0001.384] I\> Size of crypto header is 8192  
> [0001.388] I\> Size of crypto header is 8192  
> [0001.392] I\> strt\_pg\_num(6400) num\_of\_pgs(16) read\_buf(0x800fe000)  
> [0001.398] I\> BCH of NVDEC read from storage  
> [0001.402] I\> BCH address is : 0x800fe000  
> [0001.406] I\> NVDEC header integrity check is success  
> [0001.411] I\> Binary magic in BCH component 0 is NDEC  
> [0001.416] I\> component binary type is 7  
> [0001.419] I\> Size of crypto header is 8192  
> [0001.423] I\> strt\_pg\_num(6416) num\_of\_pgs(560) read\_buf(0x80000000)  
> [0001.432] I\> NVDEC binary is read from storage  
> [0001.437] I\> NVDEC binary integrity check is success  
> [0001.442] I\> Binary NVDEC loaded successfully at 0x80000000 (0x46000)  
> [0001.448] I\> Size of crypto header is 8192  
> [0001.460] I\> Task: Load tsec-fw  
> [0001.463] I\> TSEC-FW load support not enabled  
> [0001.467] I\> Task: GPIO interrupt map  
> [0001.471] I\> Task: SC7 context save  
> [0001.474] I\> Slot: 0  
> [0001.476] I\> Binary[27] block-0 (partition size: 0x100000)  
> [0001.481] I\> Binary name: BR\_BCT  
> [0001.484] I\> Size of crypto header is 8192  
> [0001.488] I\> Size of crypto header is 8192  
> [0001.492] I\> Size of crypto header is 8192  
> [0001.496] I\> strt\_pg\_num(0) num\_of\_pgs(16) read\_buf(0xa0000000)  
> [0001.502] I\> BR\_BCT binary is read from storage  
> [0001.507] I\> BR\_BCT binary integrity check is success  
> [0001.511] I\> Binary BR\_BCT loaded successfully at 0xa0000000 (0x2000)  
> [0001.518] I\> Slot: 0  
> [0001.520] I\> Binary[13] block-23808 (partition size: 0x30000)  
> [0001.525] I\> Binary name: SC7-FW  
> [0001.528] I\> Size of crypto header is 8192  
> [0001.532] I\> Size of crypto header is 8192  
> [0001.536] I\> Size of crypto header is 8192  
> [0001.540] I\> Size of crypto header is 8192  
> [0001.544] I\> strt\_pg\_num(23808) num\_of\_pgs(16) read\_buf(0xa0002000)  
> [0001.550] I\> BCH of SC7-FW read from storage  
> [0001.554] I\> BCH address is : 0xa0002000  
> [0001.558] I\> SC7-FW header integrity check is success  
> [0001.563] I\> Binary magic in BCH component 0 is WB0B  
> [0001.568] I\> component binary type is 13  
> [0001.572] I\> Size of crypto header is 8192  
> [0001.576] I\> strt\_pg\_num(23824) num\_of\_pgs(349) read\_buf(0xa0004000)  
> [0001.584] I\> SC7-FW binary is read from storage  
> [0001.589] I\> SC7-FW binary integrity check is success  
> [0001.594] I\> Binary SC7-FW loaded successfully at 0xa0004000 (0x2b920)  
> [0001.600] I\> Slot: 0  
> [0001.602] I\> Binary[22] block-24192 (partition size: 0x30000)  
> [0001.608] I\> Binary name: PSC\_RF  
> [0001.611] I\> Size of crypto header is 8192  
> [0001.615] I\> Size of crypto header is 8192  
> [0001.618] I\> Size of crypto header is 8192  
> [0001.622] I\> Size of crypto header is 8192  
> [0001.626] I\> strt\_pg\_num(24192) num\_of\_pgs(16) read\_buf(0xa002f920)  
> [0001.633] I\> BCH of PSC\_RF read from storage  
> [0001.637] I\> BCH address is : 0xa002f920  
> [0001.641] I\> PSC\_RF header integrity check is success  
> [0001.645] I\> Binary magic in BCH component 0 is PSCR  
> [0001.650] I\> component binary type is 22  
> [0001.654] I\> Size of crypto header is 8192  
> [0001.658] I\> strt\_pg\_num(24208) num\_of\_pgs(224) read\_buf(0xa0031920)  
> [0001.665] I\> PSC\_RF binary is read from storage  
> [0001.670] I\> PSC\_RF binary integrity check is success  
> [0001.675] I\> Binary PSC\_RF loaded successfully at 0xa0031920 (0x1be60)  
> [0001.684] I\> Task: Save WP0 payload to SC7 ctx  
> [0001.689] I\> Task: Load MB2rf binary to SC7 ctx  
> [0001.693] I\> Slot: 0  
> [0001.695] I\> Binary[14] block-24576 (partition size: 0x20000)  
> [0001.701] I\> Binary name: MB2\_RF  
> [0001.704] I\> Size of crypto header is 8192  
> [0001.708] I\> Size of crypto header is 8192  
> [0001.712] I\> Size of crypto header is 8192  
> [0001.715] I\> Size of crypto header is 8192  
> [0001.719] I\> strt\_pg\_num(24576) num\_of\_pgs(16) read\_buf(0xa00d5d10)  
> [0001.726] I\> BCH of MB2\_RF read from storage  
> [0001.730] I\> BCH address is : 0xa00d5d10  
> [0001.734] I\> MB2\_RF header integrity check is success  
> [0001.739] I\> Binary magic in BCH component 0 is MB2R  
> [0001.743] I\> component binary type is 14  
> [0001.747] I\> Size of crypto header is 8192  
> [0001.751] I\> strt\_pg\_num(24592) num\_of\_pgs(224) read\_buf(0xa00d7d10)  
> [0001.759] I\> MB2\_RF binary is read from storage  
> [0001.763] I\> MB2\_RF binary integrity check is success  
> [0001.768] I\> Binary MB2\_RF loaded successfully at 0xa00d7d10 (0x1bf30)  
> [0001.774] I\> Task: Save fuse alias data to SC7 ctx  
> [0001.779] I\> Task: Save PMIC data to SC7 ctx  
> [0001.783] I\> Task: Save Pinmux data to SC7 ctx  
> [0001.787] I\> Task: Save Pad Voltage data to SC7 ctx  
> [0001.792] I\> Task: Save controller prod data to SC7 ctx  
> [0001.797] I\> Task: Save prod cfg data to SC7 ctx  
> [0001.802] I\> Task: Save I2C bus freq data to SC7 ctx  
> [0001.807] I\> Task: Save SOCTherm data to SC7 ctx  
> [0001.811] I\> Task: Save FMON data to SC7 ctx  
> [0001.815] I\> Task: Save VMON data to SC7 ctx  
> [0001.819] I\> Task: Save TZDRAM data to SC7 ctx  
> [0001.823] I\> Task: Save GPIO int data to SC7 ctx  
> [0001.828] I\> Task: Save clock data to SC7 ctx  
> [0001.832] I\> Task: Save debug data to SC7 ctx  
> [0001.836] I\> Task: Save MBWT data to SC7 ctx  
> [0001.844] I\> SC7 context save done  
> [0001.848] I\> Task: Load MB2/Applet/FSKP  
> [0001.851] I\> Loading MB2  
> [0001.854] I\> Slot: 0  
> [0001.856] I\> Binary[6] block-8448 (partition size: 0x80000)  
> [0001.861] I\> Binary name: MB2  
> [0001.864] I\> Size of crypto header is 8192  
> [0001.868] I\> Size of crypto header is 8192  
> [0001.872] I\> strt\_pg\_num(8448) num\_of\_pgs(16) read\_buf(0x8007e000)  
> [0001.878] I\> BCH of MB2 read from storage  
> [0001.882] I\> BCH address is : 0x8007e000  
> [0001.886] I\> MB2 header integrity check is success  
> [0001.890] I\> Binary magic in BCH component 0 is MB2B  
> [0001.895] I\> component binary type is 6  
> [0001.899] I\> Size of crypto header is 8192  
> [0001.903] I\> strt\_pg\_num(8464) num\_of\_pgs(844) read\_buf(0x80000000)  
> [0001.914] I\> MB2 binary is read from storage  
> [0001.919] I\> MB2 binary integrity check is success  
> [0001.923] I\> Binary MB2 loaded successfully at 0x80000000 (0x696a0)  
> [0001.929] I\> Task: Map CCPLEX SHARED carveout  
> [0001.934] I\> Task: Prepare MB2 params  
> [0001.937] I\> Task: Dram ecc test  
> [0001.940] I\> Task: Misc NV security settings  
> [0001.945] I\> NVDEC sticky bits programming done  
> [0001.949] I\> Successfully powergated NVDEC  
> [0001.953] I\> Task: Disable/Reload WDT  
> [0001.957] I\> Task: Program misc carveouts  
> [0001.960] I\> Program IPC carveouts  
> [0001.964] I\> Task: Disable SCPM/POD reset  
> [0001.968] I\> SLCG Global override status := 0x0  
> [0001.972] I\> MB1: MSS reconfig completed  
> I\> MB2 (version: 0.0.0.0-t234-54845784-af79ed0a)  
> I\> t234-A01-0-Silicon (0x12347)  
> I\> Boot-mode : Coldboot  
> I\> Emulation:  
> I\> Entry timestamp: 0x001e82d8  
> I\> Regular heap: [base:0x40040000, size:0x10000]  
> I\> DMA heap: [base:0x82e000000, size:0x800000]  
> I\> Task: SE error check  
> I\> Task: Crypto init  
> I\> Task: MB2 Params integrity check  
> I\> Task: Enable CCPLEX WDT 5th expiry  
> I\> Task: ARI update carveout TZDRAM  
> I\> Task: Configure OEM set LA/PTSA values  
> I\> Task: Check MC errors  
> I\> Task: Enable hot-plug capability  
> I\> Task: PSC mailbox init  
> I\> Task: Enable clock for external modules  
> I\> Task: Measured Boot init  
> I\> Task: fTPM silicon identity init  
> I\> fTPM is not enabled.  
> I\> Task: OEM SC7 context save init  
> I\> Task: I2C register  
> I\> Task: Map CCPLEX\_INTERWORLD\_SHMEM carveout  
> I\> Task: Program CBB PCIE AMAP regions  
> I\> Task: Boot device init  
> I\> Boot\_device: QSPI\_FLASH instance: 0  
> I\> Qspi clock source : pllc\_out0  
> I\> QSPI Flash: Macronix 64MB  
> I\> QSPI-0l initialized successfully  
> I\> Secondary storage device: QSPI\_FLASH instance: 0  
> I\> Secondary storage device: SDMMC\_USER instance: 3  
> I\> sdmmc HS400 mode enabled  
> I\> Task: Partition Manager Init  
> I\> strt\_pg\_num(1) num\_of\_pgs(1) read\_buf(0x82e001000)  
> I\> strt\_pg\_num(131071) num\_of\_pgs(1) read\_buf(0x82e001000)  
> I\> strt\_pg\_num(131039) num\_of\_pgs(32) read\_buf(0x82e001200)  
> I\> Found 60 partitions in QSPI\_FLASH (instance 0)  
> W\> Cannot find any partition table for 00000003  
> W\> PARTITION\_MANAGER: Failed to publish partition.  
> I\> Found 15 partitions in SDMMC\_USER (instance 3)  
> I\> Task: Pass DRAM ECC PRL Flag to FSI  
> I\> Task: Load and authenticate registered FWs  
> I\> Task: Load AUXP FWs  
> I\> Successfully register SPE FW load task with MB2 loader  
> I\> Successfully register RCE FW load task with MB2 loader  
> I\> Successfully register DCE FW load task with MB2 loader  
> I\> Unpowergating APE  
> I\> Unpowergate done  
> I\> Successfully register APE FW load task with MB2 loader  
> I\> Skipping FSI FW load  
> I\> Successfully register XUSB FW load task with MB2 loader  
> I\> Successfully register PVA FW load task with MB2 loader  
> I\> Partition name: A\_spe-fw  
> I\> Size of partition: 589824  
> I\> Binary@ device:3/0 block-55040 (partition size: 0x90000), name: A\_spe-fw  
> I\> strt\_pg\_num(55040) num\_of\_pgs(16) read\_buf(0x40066880)  
> I\> strt\_pg\_num(55056) num\_of\_pgs(512) read\_buf(0x82d600000)  
> I\> Partition name: A\_rce-fw  
> I\> Size of partition: 1048576  
> I\> Binary@ device:3/0 block-56192 (partition size: 0x100000), name: A\_rce-fw  
> I\> strt\_pg\_num(56192) num\_of\_pgs(16) read\_buf(0x40066880)  
> I\> strt\_pg\_num(56208) num\_of\_pgs(880) read\_buf(0x82d200000)  
> I\> spe: Authentication Finalize Done  
> I\> Binary spe loaded successfully at 0x82d600000  
> I\> Partition name: A\_dce-fw  
> I\> Size of partition: 5242880  
> I\> Binary@ device:3/0 block-44800 (partition size: 0x500000), name: A\_dce-fw  
> I\> strt\_pg\_num(44800) num\_of\_pgs(16) read\_buf(0x40066880)  
> I\> rce: Authentication Finalize Done  
> I\> Binary rce loaded successfully at 0x82d200000  
> I\> Successfully register RCE FW context save task with MB2 loader  
> I\> dce : oem authentication of header done  
> I\> strt\_pg\_num(44816) num\_of\_pgs(1) read\_buf(0x82e1403d8)  
> I\> strt\_pg\_num(44816) num\_of\_pgs(8) read\_buf(0x82e1403d8)  
> I\> dce : meta-blob integrity check is success.  
> I\> strt\_pg\_num(44824) num\_of\_pgs(512) read\_buf(0x82e0003c0)  
> I\> strt\_pg\_num(45336) num\_of\_pgs(512) read\_buf(0x82e0403c0)  
> I\> dce : will be decompressed at 0x836000000  
> I\> version 1 Bin 1 BCheckSum 0 content\_size 0 Content ChkSum 1 reserved\_00 0  
> I\> Reserved10 0 BlockMaxSize 5 Reserved11 0  
> I\> strt\_pg\_num(45848) num\_of\_pgs(512) read\_buf(0x82e0803c0)  
> I\> dce : decompressed to 12062384 bytes  
> I\> dce: plain binary integrity check is success  
> I\> Partition name: A\_adsp-fw  
> I\> Size of partition: 2097152  
> I\> Binary@ device:3/0 block-58240 (partition size: 0x200000), name: A\_adsp-fw  
> I\> strt\_pg\_num(58240) num\_of\_pgs(16) read\_buf(0x40066880)  
> I\> strt\_pg\_num(58256) num\_of\_pgs(800) read\_buf(0x838800000)  
> I\> dce: Authentication Finalize Done  
> I\> Binary dce loaded successfully at 0x836000000  
> I\> Partition name: A\_xusb-fw  
> I\> Size of partition: 262144  
> I\> Binary@ device:3/0 block-9472 (partition size: 0x40000), name: A\_xusb-fw  
> I\> strt\_pg\_num(9472) num\_of\_pgs(16) read\_buf(0x40066880)  
> I\> strt\_pg\_num(9488) num\_of\_pgs(312) read\_buf(0x82d700000)  
> I\> ape: Authentication Finalize Done  
> I\> Binary ape loaded successfully at 0x838800000  
> I\> Successfully register APE FW context save task with MB2 loader  
> I\> Partition name: A\_pva-fw  
> I\> Size of partition: 262144  
> I\> Binary@ device:3/0 block-62336 (partition size: 0x40000), name: A\_pva-fw  
> I\> strt\_pg\_num(62336) num\_of\_pgs(16) read\_buf(0x40066880)  
> I\> xusb: Authentication Finalize Done  
> I\> Binary xusb loaded successfully at 0x82d700000  
> I\> Successfully register XUSB FW context save task with MB2 loader  
> I\> pva-fw : oem authentication of header done  
> I\> strt\_pg\_num(62352) num\_of\_pgs(1) read\_buf(0x82e1403d8)  
> I\> strt\_pg\_num(62352) num\_of\_pgs(8) read\_buf(0x82e1403d8)  
> I\> pva-fw : meta-blob integrity check is success.  
> I\> strt\_pg\_num(62360) num\_of\_pgs(512) read\_buf(0x82e0003c0)  
> I\> pva-fw : will be decompressed at 0x82d980000  
> I\> version 1 Bin 1 BCheckSum 0 content\_size 0 Content ChkSum 1 reserved\_00 0  
> I\> Reserved10 0 BlockMaxSize 5 Reserved11 0  
> I\> pva-fw : decompressed to 2156512 bytes  
> I\> pva-fw: plain binary integrity check is success  
> I\> pva-fw: Authentication Finalize Done  
> I\> Binary pva-fw loaded successfully at 0x82d980000  
> I\> Successfully register PVA FW context save task with MB2 loader  
> I\> Task: Check MC errors  
> I\> Task: Carveout setup  
> I\> Program remaining OEM carveouts  
> I\> Task: Enable FSITHERM  
> I\> Task: Enable FSI VMON  
> I\> FSI VMON: FSI Vmon re-calibration and fine tuning done  
> I\> Task: Validate FSI Therm readings  
> I\> Task: Restore XUSB sec  
> I\> Task: Enable FSI SE clock  
> I\> Enable FSI-SE clock…  
> I\> Task: Initialize SBSA UART CAR  
> I\> Task: Initialize CPUBL Params  
> I\> CPUBL-params @ 0x832000000  
> I\> Task: Ratchet update  
> W\> Skip ratchet update - OPTIN fuse not set  
> I\> Task: Prepare eeprom data  
> I\> Task: FSI padctl context save  
> I\> Task: Unpowergate APE  
> W\> mb2\_unpowergate\_ape: skip! APE is in unpowergated state  
> I\> Task: Memctrl reconfig pending clients  
> I\> Task: OEM firewalls  
> I\> OEM firewalls configured  
> I\> Task: Powergate APE  
> I\> Powergating APE  
> I\> Powergate done  
> I\> Task: OEM firewall restore saved settings  
> I\> Task: Unhalt AUXPs  
> I\> Unhalting SPE..  
> I\> Enabling combined UART  
> ▒▒▒▒spe: early\_init  
> ▒▒▒▒vic initialized  
> ▒▒▒▒tsc initialized  
> ▒▒▒▒aon lic initialized  
> ▒▒▒▒spe: tag is 5243985d1b1eb3f06fac6d36bd7e74ac  
> ▒▒▒▒spe: SafeRTOS v8.4  
> ▒▒▒▒spe: init  
> ▒▒▒▒scheduler initialized  
> ▒▒▒▒aon hsp initialized  
> ▒▒▒▒tag initialized  
> ▒▒▒▒tcu initialized  
> ▒▒▒▒bpmp ipc initialized  
> ▒▒▒▒spe: late init  
> ▒▒▒▒cpu\_nic clock initialized  
> ▒▒▒▒apb clock initialized  
> ▒▒▒▒pm initialized  
> ▒▒▒▒bpmp hsp initialized  
> ▒▒▒▒top1 hsp initialized  
> ▒▒▒▒ccplex ipc initialized  
> ▒▒▒▒spe: start scheduler  
> ▒▒▒▒  
> I\> Task: Trigger mailbox for PSC-BL1 exit  
> I\> Sending opcode 0x4d420802 to psc  
> I\> Received ACK from psc  
> I\> Task: Start secure NOR provision  
> I\> Skip Secure NOR provisioning  
> I\> Task: Trigger load FSI keyblob  
> I\> Skipping FSI key blob copy  
> I\> Task: Complete load FSI keyblob  
> I\> Skipping FSI key blob copy  
> I\> Task: MB2-PSC\_FW Key Manager Init  
> I\> Sending opcode OP\_PSC\_KEY\_MANAGER to psc-fw  
> I\> Sending opcode 0x4b45594d to p▒▒  
> hwwdt\_init: WDT boot cfg 0x710010 sts 0x10  
> bpmp: socket 0  
> bpmp: base binary md5 is 3b0e1a33cf85c7f62a7e8b93c2af97ed  
> bpmp: combined binary md5 is 2aafe334513692db071cfc4bbbaf4115  
> bpmp: firmware tag is 2aafe334513692db071c-3b0e1a33cf8  
> initialized vwdt  
> initialized mail\_early  
> initialized fuse  
> initialized vfrel  
> initialized adc  
> fmon\_populate\_monitors: found 199 monitors  
> initialized fmon  
> initialized mc  
> initialized reset  
> initialized uphy\_early  
> initialized emc\_early  
> initialized pm  
> 465 clocks registered  
> initialized clk\_mach  
> initialized clk\_cal\_early  
> initialized clk\_mach\_early\_config  
> initialized io\_dpd  
> initialized soctherm  
> initialized regime  
> initialized i2c  
> vrmon\_dt\_init: vrmon node not found  
> vrmon\_chk\_boot\_state: found 0 rail monitors  
> initialized vrmon  
> initialized regulator  
> ▒▒sc  
> I\> Received ACK from psc  
> I\> Task: Unhalt FSI  
> I\> FSI unhalt skipped  
> I\> Task: Unhalt AUXPs  
> I\> Unhalting RCE  
> I\> RCE unhalt successful  
> I\> Unhalting DCE  
> I\> DCE unhalt successful  
> I\> APE unhalt skipped  
> I\> Task: Load HV/CPUBL  
> I\> Task: Load TOS  
> I\> Task: Trigger l▒▒initialized avfs\_clk\_platform  
> initialized powergate  
> ▒▒[2.576343] Camera-FW on t234-rce-safe started  
> ▒▒oad▒▒TCU early console enabled.  
> ▒▒initialized dvs  
> initialized clk\_mach\_config  
> initialized suspend  
> initialized strap  
> initialized mce\_dbell  
> ▒▒ TSEC leyblob  
> I\> Sending opcode 0x53535452 to psc  
> ▒▒  
> ▒▒I\> Sent opcode to psc  
> I\> Task: Load and authenticate registered FWs  
> I\> Partition name: A\_cpu-bootloader  
> I\> Size of partition: 3670016  
> I\> Binary@ device:3/0 block-24832 (partition size: 0x380000), name: A\_cpu-bootloader  
> ▒▒DCE Started  
> ▒▒I\> strt\_pg\_num(24832) num\_of\_pgs(16) read\_buf(0x40066880)  
> I\> cpubl : oem authentication of header done  
> I\> strt\_pg\_num(24848) num\_of\_pgs(1) read\_buf(0x82e143f98)  
> I\> strt\_pg\_num(24848) num\_of\_pgs(8) read\_buf(0x82e143f98)  
> ▒▒DCE\_R5\_Init  
> ▒▒I\> cpubl : meta-blob integrity check is success.  
> I\> ▒▒initialized emc  
> initialized emc\_mrq  
> ▒▒strt\_pg\_num(24856) num\_of\_pgs(512) read\_buf(0x82▒▒initialized clk\_cal
> 
> FATAL ERROR [FILE=platform/drivers/uphy/uphy-tegra234-dt.c, ERR\_UID=2203]: invalid gbe0-enable-10g  
> r0\_usr 0x5009a2ca  
> r1\_usr 0x0000089b  
> r2\_usr 0x5009a2f3  
> r3\_usr 0x50181f50  
> r4\_usr 0x50001ff4  
> r5\_usr 0x5009a2f3  
> r6\_usr 0x0000089b  
> r7\_usr 0x5009a2ca  
> r8\_usr 0x50181f50 r8\_fiq 0x00000000  
> r9\_usr 0x00000000 r9\_fiq 0x00000000  
> r10\_usr 0x50181f88 r10\_fiq 0x00000000  
> r11\_usr 0x500036a5 r11\_fiq 0x00000000  
> r12\_usr 0x00000000 r12\_fiq 0x00000000  
> sp\_usr 0x50181f28 sp\_fiq 0x50010820 sp\_irq 0x50010c00  
> sp\_svc 0x50011400 sp\_abt 0x50010800 sp\_und 0x50010770  
> lr\_usr 0x50003179 lr\_fiq 0x00000000 lr\_irq 0x50004378  
> lr\_svc 0x5000a550 lr\_abt 0x00000000 lr\_und 0x50001ff8  
> pc 0x50001ff4  
> spsr 0x40000010  
> fpscr 0x20000010  
> 00: base: 50000000 size: 00800000 XN P\_RW U\_RW Non-shareable outer: WB, no WA inner: WB, no WA  
> 01: base: 00000000 size: 40000000 XN P\_RW U\_RW Shareable strongly-ordered  
> 02: base: 00000000 size: 00000040 X P\_RO U\_NA Non-shareable outer: WB, no WA inner: WB, no WA  
> 03: base: 50000000 size: 00010000 X P\_RO U\_RO Non-shareable outer: WB, no WA inner: WB, no WA  
> 04.1: base: 50020000 size: 00020000 X P\_RO U\_RO Non-shareable outer: WB, no WA inner: WB, no WA  
> 04.2: base: 50040000 size: 00020000 X P\_RO U\_RO Non-shareable outer: WB, no WA inner: WB, no WA  
> 04.3: base: 50060000 size: 00020000 X P\_RO U\_RO Non-shareable outer: WB, no WA inner: WB, no WA  
> 04.4: base: 50080000 size: 00020000 X P\_RO U\_RO Non-shareable outer: WB, no WA inner: WB, no WA  
> 04.5: base: 500a0000 size: 00020000 X P\_RO U\_RO Non-shareable outer: WB, no WA inner: WB, no WA  
> 04.6: base: 500c0000 size: 00020000 X P\_RO U\_RO Non-shareable outer: WB, no WA inner: WB, no WA  
> 05.1: base: 500c4000 size: 00004000 XN P\_RW U\_RW Non-shareable outer: WB, no WA inner: WB, no WA  
> 05.2: base: 500c8000 size: 00004000 XN P\_RW U\_RW Non-shareable outer: WB, no WA inner: WB, no WA  
> 05.3: base: 500cc000 size: 00004000 XN P\_RW U\_RW Non-shareable outer: WB, no WA inner: WB, no WA  
> 05.4: base: 500d0000 size: 00004000 XN P\_RW U\_RW Non-shareable outer: WB, no WA inner: WB, no WA  
> 05.5: base: 500d4000 size: 00004000 XN P\_RW U\_RW Non-shareable outer: WB, no WA inner: WB, no WA  
> 05.6: base: 500d8000 size: 00004000 XN P\_RW U\_RW Non-shareable outer: WB, no WA inner: WB, no WA  
> 05.7: base: 500dc000 size: 00004000 XN P\_RW U\_RW Non-shareable outer: WB, no WA inner: WB, no WA  
> 06: base: 50180000 size: 00080000 XN P\_RO U\_NA Non-shareable outer: WB, no WA inner: WB, no WA  
> 07: base: 50780000 size: 00080000 XN P\_RO U\_RO Non-shareable outer: WB, no WA inner: WB, no WA  
> 08: base: 50202000 size: 00002000 XN P\_RW U\_RW Non-shareable outer: WT, no WA inner: WT, no WA  
> 10: base: 40070000 size: 00010000 XN P\_RW U\_RW Non-shareable outer: WB, no WA inner: WB, no WA  
> 15: base: 50180000 size: 00002000 XN P\_RW U\_RW Non-shareable outer: WB, no WA inner: WB, no WA  
> Bootstrap@0x50218f40 sp 0x50181f28 stack: 50180000 - 50181ffc  
> Per task regions for Bootstrap  
> 04: base: 50180000 size: 00002000 XN P\_RW U\_RW Non-shareable outer: WB, no WA inner: WB, no WA  
> Enable MMIO: 1, Enable data R/W: 1  
> call stack:  
> sp 0x50181f28 pc 0x50001ff4  
> sp 0x50181f28 pc 0x50003178  
> sp 0x50181f40 pc 0x5006d712  
> sp 0x50181f78 pc 0x5002f1d4  
> sp 0x50181fb8 pc 0x5002dc40  
> sp 0x50181fe0 pc 0x5006947e  
> sp 0x50181ff8 pc 0xaaaaaaaa  
> eht\_idx\_find: 0xaaaaaaaa not a valid code address  
> no eidx for 0xaaaaaaaa  
> ▒▒e003f80)  
> ▒▒MPU enabled  
> DCE\_SW\_Init  
> ▒▒I\> strt\_pg\_num(25368) num\_of\_pgs(512) read\_buf(0x82e043f80)  
> I\> cpubl : will be decompressed at 0x82c800000  
> I\> version 1 Bin 1 BCheckSum 0 content\_size 0 Content ChkSum 1 reserved\_00 0  
> I\> Reserved10 0 BlockMaxSize 5 Reserved11 0  
> I\> strt\_pg\_num(25880) num\_of\_pgs(512) read\_buf(0x82e083f80)  
> I\> strt\_pg\_num(26392) num\_of\_pgs(512) read\_buf(0x82e0c3f80)  
> I\> strt\_pg\_num(26904) num\_of\_pgs(512) read\_buf(0x82e103f80)  
> I\> strt\_pg\_num(27416) num\_of\_pgs(512) read\_buf(0x82e003f80)  
> I\> strt\_pg\_num(27928) num\_of\_pgs(512) read\_buf(0x82e043f80)  
> I\> strt\_pg\_num(28440) num\_of\_pgs(512) read\_buf(0x82e083f80)  
> I\> strt\_pg\_num(28952) num\_of\_pgs(512) read\_buf(0x82e0c3f80)  
> I\> strt\_pg\_num(29464) num\_of\_pgs(512) read\_buf(0x82e103f80)  
> I\> strt\_pg\_num(29976) num\_of\_pgs(512) read\_buf(0x82e003f80)  
> I\> strt\_pg\_num(30488) num\_of\_pgs(512) read\_buf(0x82e043f80)  
> I\> strt\_pg\_num(31000) num\_of\_pgs(512) read\_buf(0x82e083f80)  
> I\> cpubl : decompressed to 3649664 bytes  
> I\> cpubl: plain binary integrity check is success  
> I\> Partition name: A\_secure-os  
> I\> Size of partition: 4194304  
> I\> Binary@ device:3/0 block-32000 (partition size: 0x400000), name: A\_secure-os  
> I\> strt\_pg\_num(32000) num\_of\_pgs(16) read\_buf(0x40066880)  
> I\> strt\_pg\_num(32016) num\_of\_pgs(3176) read\_buf(0x83fd73000)  
> I\> MB2-params @ 0x40060000  
> I\> NSDRAM carveout base: 0x80000000, size: 0x7acdf0000  
> I\> cpubl\_params: nsdram: carveout: 1, encryption: 1  
> I\> cpubl: Authentication Finalize Done  
> I\> Binary cpubl loaded successfully at 0x82c800000  
> I\> tos: Authentication Finalize Done  
> I\> Binary tos loaded successfully at 0x83fd73000  
> I\> Relocating OP-TEE dtb from: 0x83feff0f0 to 0x83c040020, size: 0x2889  
> I\> [0] START: 0x80000000, SIZE: 0x7acdf0000  
> I\> [1] START: 0x832000000, SIZE: 0x2000000  
> I\> Setting NS memory ranges to OP-TEE dtb finished.  
> I\> Partition name: A\_eks  
> I\> Size of partition: 262144  
> I\> Binary@ device:3/0 block-44288 (partition size: 0x40000), name: A\_eks  
> I\> strt\_pg\_num(44288) num\_of\_pgs(16) read\_buf(0x40066880)  
> I\> strt\_pg\_num(44304) num\_of\_pgs(8) read\_buf(0x83c020000)  
> I\> eks: Authentication Finalize Done  
> I\> Binary eks loaded successfully at 0x83c020000  
> I\> EKB detected (length: 0x410) @ VA:0x83c020000  
> I\> Task: Add cpubl params integrity check  
> I\> Added cpubl params digest.  
> I\> Task: Prepare TOS params  
> I\> Setting EKB blob info to OPTEE dtb finished.  
> I\> Setting OPTEE arg3: 0x83c040020  
> I\> NVRNG: Health check success  
> I\> NVRNG: Health check success  
> I\> Task: OEM SC7 context save  
> I\> OEM sc7 context saved  
> I\> Task: Disable MSS perf stats  
> I\> Task: Program display sticky bits  
> I\> Task: Storage device deinit  
> I\> Task: SMMU external bypass disable  
> I\> Task: SMMU init  
> I\> Task: Program GICv3 registers  
> I\> Task: Audit firewall settings  
> I\> Task: Bootchain failure check  
> I\> Current Boot-Chain Slot: 0  
> I\> BR-BCT Boot-Chain is 0, and status is 1. Set UPDATE\_BRBCT bit to 0  
> I\> Task: Burn RESERVED\_ODM0 fuse  
> I\> Task: Lock fusing  
> I\> Task: Clear dec source key  
> I\> MB2 finished
> 
> ▒▒NOTICE: BL31: v2.8(release):e12e3fa93  
> NOTICE: BL31: Built : 09:56:21, May 6 2024  
> I/TC:  
> I/TC: Non-secure external DT found  
> I/TC: OP-TEE version: 3.22 (gcc version 11.3.0 (Buildroot 2022.08)) #2 Mon May 6 17:07:49 UTC 2024 aarch64  
> I/TC: WARNING: This OP-TEE configuration might be insecure!  
> I/TC: WARNING: Please check [Porting guidelines — OP-TEE documentation documentation](https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html)  
> I/TC: Primary CPU initializing  
> I/TC: Test OEM keys are being used. This is insecure for shipping products!  
> I/TC: Primary CPU switching to normal world boot  
> ▒▒  
> Jetson UEFI firmware (version 36.3.0-gcid-36191598 built on 2024-05-06T16:58:59+00:00)  
> ▒▒ERROR: camera-ip/isp5/isp5.c:2031 [isp5\_pm\_init] “ERROR: Failed to turn isp1 power on”  
> BUG: core/init/init.c:86 [init\_all] “\*\*\* FIRMWARE INIT FAILED AT LEVEL 95 \*\*\*”  
> ▒▒  
> ▒▒Admin Task Init  
> Admin Task Init complete  
> Print Task Init  
> RM Task Init  
> SHA Task Init  
> Admin Task Started  
> DCE SC7 SHA Enabled  
> RM Task Started  
> RM Task Running  
> ▒▒

[orin\_mpg\_v3\_log\_2.txt](https://forums.developer.nvidia.com/uploads/short-url/51RrRA7r6uNxMVB58fIhS7KAxEi.txt) (36.6 KB)

---

<div class="post-metadata">

**Author:** ![WayneWWW](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/waynewww/32/14043_2.png) [@WayneWWW](https://forums.developer.nvidia.com/u/WayneWWW)\
**Post date:** [April 15, 2025, 8:49am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/12 "2025-04-15T08:49:05Z")

</div>

```auto

FATAL ERROR [FILE=platform/drivers/uphy/uphy-tegra234-dt.c, ERR_UID=2203]: invalid gbe0-enable-10g

```

This is the error log you got. If you do not have MGBE on the board anymore, you should remove that from ODMDATA.

Also, for that “demo boards”, if you are talking about NV devkit, please take a picture and share steps for how you dump the log.  
You are talking about something that others are using everyday without any issue. Thus, I think it is more likely due to a wrong usage on your side.

---

<div class="post-metadata">

**Author:** ![jackbuffett](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jackbuffett](https://forums.developer.nvidia.com/u/jackbuffett)\
**Post date:** [April 15, 2025, 9:19am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/13 "2025-04-15T09:19:43Z")

</div>

Yes, I could be mistaken. Next time, I will take a picture.  
Log is our board, not the NV demoboard.

 ![image](https://global.discourse-cdn.com/nvidia/original/4X/5/5/2/5528e34c9cc50d30cb1e9ce6b267bdb35007544f.jpeg)

---

<div class="post-metadata">

**Author:** ![WayneWWW](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/waynewww/32/14043_2.png) [@WayneWWW](https://forums.developer.nvidia.com/u/WayneWWW)\
**Post date:** [April 15, 2025, 9:21am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/14 "2025-04-15T09:21:58Z")

</div>

Ok. I just to want comment that you could dump log from devkit board in case you didn’t know how to.  
If you know how to dump a log on devkit, then we are good here.

---

<div class="post-metadata">

**Author:** ![jackbuffett](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jackbuffett](https://forums.developer.nvidia.com/u/jackbuffett)\
**Post date:** [April 15, 2025, 9:39am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/15 "2025-04-15T09:39:49Z")

</div>

OK, I see

---

<div class="post-metadata">

**Author:** ![jackbuffett](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jackbuffett](https://forums.developer.nvidia.com/u/jackbuffett)\
**Post date:** [April 15, 2025, 9:41am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/16 "2025-04-15T09:41:10Z")

</div>

Can you provide ATSAMD21G16B-AU firmware?  
Currently I’m using a chip transferred from an NV demo board, so only one board is working.

---

<div class="post-metadata">

**Author:** ![WayneWWW](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/waynewww/32/14043_2.png) [@WayneWWW](https://forums.developer.nvidia.com/u/WayneWWW)\
**Post date:** [April 15, 2025, 10:00am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/17 "2025-04-15T10:00:38Z")

</div>

> [@jackbuffett](#):
>
> ATSAMD21G16B-AU

> [@Where can I find the firmware of EFM/ATSAMD21G16B-AU](https://forums.developer.nvidia.com/t/where-can-i-find-the-firmware-of-efm-atsamd21g16b-au/277718/4):
>
> just find the similar thread [Does anyone have the firmware of ATSAMD21G16B on Jetson\_AGX\_Orin\_DevKit\_Carrier\_Board](https://forums.developer.nvidia.com/t/does-anyone-have-the-firmware-of-atsamd21g16b-on-jetson-agx-orin-devkit-carrier-board/266746), if ATSAMD21G16B-AU is only used for USB to serial port debugging, then this firmware is not needed. We will adopt our own debugging scheme for debug purpse

please file a new topic if original issue is already gone.

---

<div class="post-metadata">

**Author:** ![jackbuffett](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jackbuffett](https://forums.developer.nvidia.com/u/jackbuffett)\
**Post date:** [April 16, 2025, 1:38am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/18 "2025-04-16T01:38:44Z")

</div>

I have seen this content too.  
We also need it for debugging, so we asked.  
I understand that it is difficult to provide.

---

<div class="post-metadata">

**Author:** ![system](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/system/32/68080_2.png) [@system](https://forums.developer.nvidia.com/u/system)\
**Post date:** [May 21, 2025, 3:36am UTC](https://forums.developer.nvidia.com/t/hw-orin-config-2-board/330114/20 "2025-05-21T03:36:16Z")

</div>

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