I want to change the minimum pulse of PWM

Hi.

I want to use PWM under the following conditions.
period: 10.24ms
resolution: 2048
minimum pulse: 5μs

I set it as below, but PWM was not output.

echo 10240000 > /sys/devices/7000a000.pwm/pwm/pwmchip0/pwm0/period
echo 5000 > /sys/devices/7000a000.pwm/pwm/pwmchip0/pwm0/duty_cycle
echo 1 > /sys/devices/7000a000.pwm/pwm/pwmchip0/pwm0/enable

When duty_cycle is set to 2000, PWM is output, but an unintended 40 μs pulse is output.
How can I output a PWM with a minimum pulse of 5 μs?

Sorry for the late response, is this still an issue to support? Thanks

hello k-irisa,

may I know what’s the actual use-case;
this duty_cycle is less than 1% of the period settings.

Hi JerryChang.

Used to adjust the brightness of the LCD.
I want to set the resolution of the period to 2048.

hello k-irisa,

BTW, don’t the backlight start blinking with such low PWM clock?

Hi JerryChang.

It did not blink when the period was 1024 ms and the resolution was 256.
Can the resolution be 2048?

Hi kayccc.

This is a issue that I still want to support.

Hi,

What kind of device is in use here? A panel?

Does the “resolution” mean the panel resolution?

Hi Wayne WWW.

Not the resolution of the panel.
I want to set the minimum duty cycle of PWM pulse (10240 μs) to 5 μs.
I want to control one PWM pulse at 1/2048.

hello k-irisa,

please share the crrent rate of pwmN (in Hz), $ cat /sys/kernel/debug/bpmp/debug/clk/pwmN/rate
could you please also check all possible clock parents,
for example, pwmN, $ cat /sys/kernel/debug/bpmp/debug/clk/pwmN/possible_parents

Hi JerryChang.

please share the crrent rate of pwmN (in Hz), $ cat /sys/kernel/debug/bpmp/debug/clk/pwmN/rate
could you please also check all possible clock parents,
for example, pwmN, $ cat /sys/kernel/debug/bpmp/debug/clk/pwmN/possible_parents

I tried to read above, but the “/ sys / kernel / debug / bpmp” directory was missing.
https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/clocks.html
I read this and it says that “Jetson AGX Xavier series and Jetson TX2 series” is supported.
How do I read it on Jetson Nano?

hello k-irisa,

please check this on Nano series, $ cat /sys/kernel/debug/clk/pwm/clk_possible_parents
you may also examine the clk_rate to check the possible rate for the PWM controller.
please note that PWM has to be divide by 256 for its max rate,
thanks

Hi JerryChang.

The dump looks like this:

$ sudo -s cat /sys/kernel/debug/clk/pwm/clk_rate
48000000
$ sudo -s cat /sys/kernel/debug/clk/pwm/clk_possible_parents
pll_p pll_c clk_32k clk_m

hello k-irisa,

you’ll need to change the PWM clock if you’re looking for lower frequency,
please try clk_32k. thanks

Hi JerryChang.

Do you know how to change the PWM clock to clk_32k?

hello k-irisa,

please refer to below,
you may check all possible clock parents of pwmN.
$ cat /sys/kernel/debug/bpmp/debug/clk/pwmN/possible_parents
and, setting a new source from those possible sources
$ echo <new_source> > /sys/kernel/debug/bpmp/debug/clk/pwmN/parent

Hi JerryChang.

Thanks for the information.
I was able to change the CLK with this setting.

$ echo <new_source> > /sys/kernel/debug/clk/pwm/clk_parent

But there was nothing I wanted to achieve.
I want to control one PWM pulse by dividing it into 2048.
I want to achieve a minimum high time of 5 μs for one pulse with a period of 10.24 ms.
I read the technical reference manual, but can one pulse only be divided into 256?

hello k-irisa,

here’s formula to calculate the possible rate of a PWM controller,
Max Rate = clock Mhz/ 256
Min Rate = clock Mhz/ (256* 2^13) (i.e. 13-bits Frequency divider (bits 0:12))

you should check whether the configurations is within the range,
if yes, period setting is in terms of nanoseconds. so frequency should be provided after Hz to ns conversion,
i.e. period = (1/rate)*10^9; duty cycle is the percentage of the period.

Hi JerryChang.

Thanks for the information.
When applied to this calculation, it becomes as follows.

Max Rate = clock Mhz/ 256 = 48MHz / 256 = 187.5kHz
period = (1/rate)*10^9 = (1/187.5k)*10^9 = 5333(ns)

In this case, do you recognize that the following conditions will not be realized because the period obtained by multiplying the duty cycle is out of range?

period : 10ms
duty cycle : 0.05% (10ms * 0.05% = 5μs)

I think it can be achieved by raising the clock, but is there a way to raise the clock?

hello k-irisa,

the device clock maximum speed is 48MHz, and it’s necessary to have it divide by 256 to generate the PWM output frequency. you may access TRM to obtain the details.
so, that’s not supported.