I want to know the guidelines for configuring decoupling capacitors

[hudson4]

Hi,
We are reviewing the AGX Orin schematic for our carrier board schematic.

As you can see below,
There are many capacitors attached, but U9’s datasheet lacks guidelines.
Based on what criteria were the capacitance values and the number of capacitors determined?
“Can you give a simple explanation?”

Thanks.

[Trumany]

Please refer to below concept schematic. The decoupling capacitors design is based on PDN simulation and validation result.

[hudson4]

"Did you use your own tool for the PDN simulation? NVIDIA doesn’t provide any tools for that, right?

[Trumany]

Yes and we don’t provide the tool. Customer should be able to do that with EDA tool too.

[raymond25]

Hi Trumany…

I’m Raymond, co-work with Hudson

We need guidance on the Decoupling Capacitance value and quantity to be applied to the VCC_SRC (SYS_VIN_HV, 12V) supply.

If we build a circuit with the conditions below, can you give me some guidance on the decoupling capacitors?

The carrier board we are designing will be powered by 12V power directly from the SMPS.

In other words, the VCC_DCIN – VCC_SRC_FET – VCC_SRC power supply will be fixed to 12V and not variable.

Also, we will not be using the x16 PCIe Connector.

So we do not want to use the VDD_12V (Page 35) of the P3737(P3737_A05_OrCAD_schematics(base_version).pdf) reference circuit.

At this time, we are asking this question because we do not see any circuit that can provide appropriate decoupling time to VCC_SRC, excluding the corresponding capacitance in the VDD_12V circuit diagram.

Thanks,
Raymond Lee

[raymond25]

Hi Trumany…

If VCC_SRC is fixed to 12V, we think the number and value of capacitors in the circuit that Hudson first captured should be somewhat smaller.

Thanks,
Raymond Lee

[Trumany]

We dont have other suggestion than the reference design on this part. You may copy the reference design or do simulation with EDA tool.