I2S Controller - Slave - Audio is more noise

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

Hello All,

In Tx2 board, in J21 connector, I2S1 pins are connected to other board I2S pins.
Here, other board, I2S controller is master and Tx2 board’s I2S controller is slave.

In device tree, how to configure the Tx2’s I2S controller is slave?

Tried the below things:

amixer cset -Dhw:1 name=“ADMAIF1 Mux” ‘I2S1’
arecord -Dhw:1,0 -f S16_LE -c 2 -r 48000 -t wav d11.wav

After this, did the playback as:

nvgstplayer-1.0 -i d11.wav

Heard much noises (90%) in audio. How to rectify this? What kind of changes are required?

-Thanks.

2

Hello All,

In Device Tree, in DAI link, it is configured as:

bitclock-slave;
frame-slave;
bitclock-noninversion;
frame-noninversion;

bclk_ratio = <0>;

What is the meaning of these values?

-Thanks.

3

Hello!

The bitclock-slave and frame-slave indicate that the codec is the bitclock and frame-clock slave. If you want the codec to be the bitclock and frame-clock master, then you need to change these to ‘bitclock-master’ and ‘frame-master’. However, when do this you also need to consider how the codec mclk is being provided to the codec. Do you know what is providing the codec mclk in the case where the codec is the bitclock and frame master?

With regard to the other properties these are …

bitclock-noninversion: bitclock is NOT inverted
frame-noninversion: frame clock is NOT inverted
bclk_ratio = <0> This sets a 1:1 ratio between the bitclock and the I2S data input/outputs. For example, if you have 16-bit samples, 2 channels at 48kHz, then the I2S data rate will be 1.538Mbps. With a 1:1 ratio, the I2S bitclock will work at 1.538MHz, if you set the ratio to 2, then it would be 3.072MHz.

Regards,
Jon

4

Hello Jon,

Thanks for the reply.

The bitclock-slave and frame-slave means that I2S controller in Nvidia Processor is Master which provides these clocks.

Please confirm this.

-Thanks.

5

Hello!

Yes that is correct. The DT bindings reflect the codec mode and so the Tegra I2S controller has the opposite configuration.

Regards,
Jon

6

Thanks for the confirmation.

7

Hello All,
In slave mode, it is working fine. It is configured as Receiver.

But I have some doubts:

  1. In register, I2S_CTRL_0, FSYNC_WIDTH (in terms of no. of bit clocks) field
  2. In register, I2S_TIMING_0, CHANNEL_BIT_CNT (I2S, LJM, RJM mode: Number of bit clocks in left or right channel.) field

These bits will be programmed only in Master mode. Since these clocks are generated by the master.
In slave mode, it does not affect anything.
Please confirm.

-Thanks.

8

Hello!

Actually the above registers are programmed in both master and slave modes. See the functions tegra210_i2s_hw_params() and tegra210_i2s_set_fmt() …

https://nv-tegra.nvidia.com/gitweb/?p=linux-nvidia.git;a=blob;f=sound/soc/tegra-alt/tegra210_i2s_alt.c;h=bcd50031a384ea8ee2ae5bfbc45b87da98003133;hb=l4t/l4t-r32.1

However, that said I did a bit of testing with a codec that is the I2S master, and it appears that although it is not necessary to program the FSYNC_WIDTH, it is necessary to program the I2S_TIMING register otherwise only noise is heard.

Hope that helps.

Regards,
Jon

9

Hello Jon,
Thanks for the reply.

10

In Slave mode, Can I get the Sample rate values from registers or other facilities?

-Thanks.

11

Hello!

I am not sure that I understand the question. The sample-rate is typically set by the application when playback/capture is initiated. The I2S registers will not indicate the sample-rate, but if Tegra is the I2S master you can always look at the clock frequency for the I2S to see what the bit clock is operating at …

sudo cat /sys/kernel/debug/clk/clk_summary

Regards,
Jon