I2S FRAME CLK to BCLK timing relationship

In looking at the output of both these signals, it would appear to me I am not getting enough delay between the edges based on the data sheet for the tlv320adc5140 chip.

I have placed in the tlv320adc5140 in BCLK polarity inversion so the edges are correct. However, if you look at this timing, even though it is at 200ns/div, they look spot on with each other

In the data sheet, I have to have a minimum of 8ns between the edges for setup time (FRAME CLK needs to be pushed out):

Screenshot 2023-08-08 at 10.51.23 AM

I’ve looked through the docs & forum, but I am not sure how to have it shift that edge out a bit.

The tlv320adc5140 does see both clocks, however, the internal syncing circuitry is having trouble staying synced which leads me to believe that it’s likely the setup time being violated probably right at the limit.

In further investigation, I think the default TDM timing coming out of the Jetson is correct and the BCLK should not be inverted in the tlv320adc5140 chip as that 1/2 cycle edge being later would meet the setup requirement.

I discovered the problem was a faulty chip. I have replaced it and now I see data coming out of the ADC.

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