In looking at the output of both these signals, it would appear to me I am not getting enough delay between the edges based on the data sheet for the tlv320adc5140 chip.
I have placed in the tlv320adc5140 in BCLK polarity inversion so the edges are correct. However, if you look at this timing, even though it is at 200ns/div, they look spot on with each other
In the data sheet, I have to have a minimum of 8ns between the edges for setup time (FRAME CLK needs to be pushed out):
I’ve looked through the docs & forum, but I am not sure how to have it shift that edge out a bit.
The tlv320adc5140 does see both clocks, however, the internal syncing circuitry is having trouble staying synced which leads me to believe that it’s likely the setup time being violated probably right at the limit.