I2S MCLK on Jetson TX2

Autonomous Machines Jetson & Embedded Systems Jetson TX2
21

Jon,

the aud_clk is now detached and has no parent clock (at the end of the list), are you sure that clk_pll_p_out1 is a valid clock shouldn’t it be clk_pll_p_out0?

Regards,

Igal

22

Hi Igal,

Yes that should be the one, but I see the following in the same file …

/* pll_p_out1 is not used for ahub for T210,T186 */
	if (data->soc < TEGRA_ASOC_UTILS_SOC_TEGRA210) {
		data->clk_pll_p_out1 = clk_get_sys(NULL, "pll_p_out1");
		if (IS_ERR(data->clk_pll_p_out1)) {
			dev_err(data->dev, "Can't retrieve clk pll_p_out1\n");
			ret = PTR_ERR(data->clk_pll_p_out1);
			goto err;
		}
	}

Can you remove this check on “if (data->soc < TEGRA_ASOC_UTILS_SOC_TEGRA210)”? The clock is defined in device-tree and so we should be able to use it.

Regards,
Jon

23

Jon, hi,

sorry but the function clk_get_sys fails.

Regards,
Igal

24

Hi Igal,

Yes of course, I did not catch that. Can you replace clk_get_sys() with tegra_alt_asoc_utils_get_clk(dev, false, “pll_p_out1”).

Regards,
Jon

25

Hi Igal,

Great, I assume that means you now have 12MHz output? I will fix the pllp clock request so this can be used as a clock parent in future releases for T210/T186.

Regards,
Jon

26

Jon,

Yes this means that I can see a clear 12[MHz] from J21 pin 7, thanks for the support.

Though, please don’t forget the bigger picture :) [url]TLV320AIC32x4 evaluation board with TX2 - Jetson TX2 - NVIDIA Developer Forums

Regards,
Igal

27