# I2S sound in Jetpack4.2.2 L4T R32.2.1 **URL:** \ **Category:** Jetson Nano\ **Created:** [October 2, 2019, 6:16pm UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675 "2019-10-02T18:16:20Z")\ **Posts on this page:** 15\ **Page:** 1
**Author:** ![yas\_its](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@yas\_its](https://forums.developer.nvidia.com/u/yas_its)\ **Post date:** [October 2, 2019, 6:16pm UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/1 "2019-10-02T18:16:20Z")
How to enable I2S sound in Jetson Nano with Linux R32.2.1. After update driver tree in R32.1, it is working fine but not working in R32.2.1 ---
**Author:** ![jonathanh](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jonathanh/32/14043_2.png) [@jonathanh](https://forums.developer.nvidia.com/u/jonathanh)\ **Post date:** [October 3, 2019, 10:07am UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/2 "2019-10-03T10:07:49Z")
Hello! If you are using the I2S interface on the 40pin expansion header, you need to ensure that the pinmux is configured to enable the I2S interface. There is a application note available that describes the process for update the pinmux. > **[customizing\_the\_jetson\_nano\_40-pin\_expansion\_header\_v1.2.pdf](https://developer.download.nvidia.com/assets/embedded/secure/jetson/Nano/docs/customizing_the_jetson_nano_40-pin_expansion_header_v1.2.pdf?6YIcEKu7BjwrXfRVwvepsmEnlBQod4d6Z6psHmrqyxIQF8gpxrRp4aKaqBPyrwzorQ1LmSw1f1Q_fsjEbMGHN8JvB9_j30wY-ETTUp6UXR1G5i8EXRYCwEAcxicESvY7E7BtFgC4H9Ph1JCDYzXpEd1bLY81K5AKPcDnocPDmr8olj6_y6WkQSmZrI7dg2k2FIsWzw5pvDvVwDNN1iWH5ti9rg)** > > 148.56 KB Regards, Jon ---
**Author:** ![yas\_its](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@yas\_its](https://forums.developer.nvidia.com/u/yas_its)\ **Post date:** [October 3, 2019, 12:03pm UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/3 "2019-10-03T12:03:19Z")
Ok Thanks for reply ---
**Author:** ![yas\_its](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@yas\_its](https://forums.developer.nvidia.com/u/yas_its)\ **Post date:** [October 4, 2019, 7:02pm UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/4 "2019-10-04T19:02:48Z")
I have completed all the steps as per [https://developer.nvidia.com/embedded/dlc/Jetson-Nano-40-Pin-Expansion-Header-1.1](https://developer.nvidia.com/embedded/dlc/Jetson-Nano-40-Pin-Expansion-Header-1.1) , but device is not booting after ‘sudo ./flash.sh jetson-nano-qspi-sd mmcblk0p1’. Only ‘NVIDIA’ logo is coming. Kindly provide Solution. Regards, Yashwant ---
**Author:** ![jonathanh](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jonathanh/32/14043_2.png) [@jonathanh](https://forums.developer.nvidia.com/u/jonathanh)\ **Post date:** [October 7, 2019, 8:17am UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/5 "2019-10-07T08:17:35Z")
Hello! We have identified a issue with the current pinmux spreadsheet for Nano where the MMC pins are not being correctly configured by default and preventing the device from booting. We are working to fix this. In the meantime, can you revert the changes you have made and make the following change only … > **[I2S audio output not working](https://forums.developer.nvidia.com/default/topic/1061108/jetson-nano/i2s-audio-output-not-working/post/5374074/)** > > Hi, I’m trying to configure nano I2S audio output as below: aud\_mclk I2S3\_LRCK I2S3\_SDATA\_IN I2S3\_SDATA\_OUT I2S3\_SCLK I’ve done some dtsi modifications, compile to DTB and signed, flash to mmcblk0p10. Build u-boot and flash via command sudo... Sorry about this. Regards, Jon ---
**Author:** ![BARO](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/baro/32/82443_2.png) [@BARO](https://forums.developer.nvidia.com/u/BARO)\ **Post date:** [October 8, 2019, 9:23am UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/6 "2019-10-08T09:23:40Z")
Hello Jonathan . this problem was solved? ---
**Author:** ![jonathanh](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jonathanh/32/14043_2.png) [@jonathanh](https://forums.developer.nvidia.com/u/jonathanh)\ **Post date:** [October 8, 2019, 9:36am UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/7 "2019-10-08T09:36:59Z")
Hello! > [@](#): > > Hello Jonathan . this problem was solved? I have not seen a new version published yet, but I will chase this. Regards, Jon ---
**Author:** ![yas\_its](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@yas\_its](https://forums.developer.nvidia.com/u/yas_its)\ **Post date:** [October 8, 2019, 9:39am UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/8 "2019-10-08T09:39:57Z")
Deaar Jon, I have modified pinmux-config-p3450-porg.h as per direction, now I2S sound is working fine. Regards, Yashwant ---
**Author:** ![yas\_its](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@yas\_its](https://forums.developer.nvidia.com/u/yas_its)\ **Post date:** [October 8, 2019, 9:49am UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/9 "2019-10-08T09:49:01Z")
I2S4 and spi1 both enabled. Working pinmux-config-p3450-porg.h file is: /\* - Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. - - SPDX-License-Identifier: GPL-2.0+ \*/ /\* - THIS FILE IS AUTO-GENERATED - DO NOT EDIT! - - To generate this file, use the tegra-pinmux-scripts tool available from - [https://github.com/NVIDIA/tegra-pinmux-scripts](https://github.com/NVIDIA/tegra-pinmux-scripts) - Run “board-to-uboot.py nano”. - Used the T210\_P3448\_SKU0\_pinmux sheet, tab B00-B01 as of 2 May 2019, v18. - NOTE: To WAR A01 \<-\> A02 Porg differences, I’ve edited this file. - ``` Removed DAP1/DAP4 pinmux programming as a WAR for A01 Porg. ``` - Also, A02 \<-\> B00/B01 diff includes CLK\_32K\_OUT, which is NC on A02, - and CC7/I1 muxes/GPIOs (both OUT1). \*/ #ifndef _PINMUX\_CONFIG\_P3450\_PORG\_H_ #define _PINMUX\_CONFIG\_P3450\_PORG\_H_ #define GPIO\_INIT(\_port, \_gpio, \_init) { .gpio = TEGRA\_GPIO(\_port, _gpio), .init = TEGRA\_GPIO\_INIT_##\_init, } static const struct tegra\_gpio\_config p3450\_porg\_gpio\_inits = { /\* port, pin, init\_val \*/ GPIO\_INIT(A, 5, IN), GPIO\_INIT(A, 6, OUT1), GPIO\_INIT(B, 4, IN), GPIO\_INIT(B, 5, IN), GPIO\_INIT(B, 6, IN), GPIO\_INIT(B, 7, IN), GPIO\_INIT(E, 6, IN), GPIO\_INIT(G, 2, IN), GPIO\_INIT(G, 3, IN), GPIO\_INIT(H, 0, OUT0), GPIO\_INIT(H, 2, IN), GPIO\_INIT(H, 3, OUT0), GPIO\_INIT(H, 4, OUT0), GPIO\_INIT(H, 5, IN), GPIO\_INIT(H, 6, IN), GPIO\_INIT(H, 7, OUT0), GPIO\_INIT(I, 0, OUT0), GPIO\_INIT(I, 1, OUT1), GPIO\_INIT(I, 2, OUT0), GPIO\_INIT(S, 5, IN), GPIO\_INIT(S, 7, OUT0), GPIO\_INIT(T, 0, OUT0), GPIO\_INIT(V, 0, IN), GPIO\_INIT(V, 1, IN), GPIO\_INIT(X, 3, OUT1), GPIO\_INIT(X, 4, IN), GPIO\_INIT(X, 5, IN), GPIO\_INIT(X, 6, IN), GPIO\_INIT(Y, 1, IN), GPIO\_INIT(Y, 2, IN), GPIO\_INIT(Z, 0, IN), GPIO\_INIT(Z, 2, IN), GPIO\_INIT(Z, 3, OUT0), GPIO\_INIT(CC, 4, IN), GPIO\_INIT(CC, 7, OUT1), GPIO\_INIT(DD, 0, IN), }; #define PINCFG(\_pingrp, \_mux, \_pull, \_tri, \_io, \_od, _e\_io\_hv) { .pingrp = PMUX\_PINGRP_##_pingrp, .func = PMUX\_FUNC_##_mux, .pull = PMUX\_PULL_##_pull, .tristate = PMUX\_TRI_##_tri, .io = PMUX\_PIN_##_io, .od = PMUX\_PIN\_OD_##_od, .e\_io\_hv = PMUX\_PIN\_E\_IO\_HV_##\_e\_io\_hv, .lock = PMUX\_PIN\_LOCK\_DEFAULT, } static const struct pmux\_pingrp\_config p3450\_porg\_pingrps = { /\* pingrp, mux, pull, tri, e\_input, od, e\_io\_hv \*/ PINCFG(PEX\_L0\_RST\_N\_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), PINCFG(PEX\_L0\_CLKREQ\_N\_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), PINCFG(PEX\_WAKE\_N\_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), PINCFG(PEX\_L1\_RST\_N\_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), PINCFG(PEX\_L1\_CLKREQ\_N\_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), PINCFG(SATA\_LED\_ACTIVE\_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(PA6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(SPI2\_MOSI\_PB4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SPI2\_MISO\_PB5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SPI2\_SCK\_PB6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SPI2\_CS0\_PB7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SPI1\_MOSI\_PC0, SPI1, DOWN, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(SPI1\_MISO\_PC1, SPI1, NORMAL, TRISTATE, INPUT, DISABLE, DEFAULT), PINCFG(SPI1\_SCK\_PC2, SPI1, DOWN, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(SPI1\_CS0\_PC3, SPI1, UP, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(SPI1\_CS1\_PC4, SPI1, UP, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(SPI4\_SCK\_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(SPI4\_CS0\_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(SPI4\_MOSI\_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(SPI4\_MISO\_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(UART3\_TX\_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(UART3\_RX\_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(UART3\_RTS\_PD3, UARTC, UP, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(UART3\_CTS\_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(DMIC1\_CLK\_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(DMIC1\_DAT\_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(DMIC2\_CLK\_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(DMIC2\_DAT\_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(DMIC3\_CLK\_PE4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(DMIC3\_DAT\_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(GEN3\_I2C\_SCL\_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), PINCFG(GEN3\_I2C\_SDA\_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), PINCFG(UART2\_TX\_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(UART2\_RX\_PG1, UARTB, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(UART2\_RTS\_PG2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(UART2\_CTS\_PG3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(WIFI\_EN\_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(WIFI\_RST\_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(WIFI\_WAKE\_AP\_PH2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(AP\_WAKE\_BT\_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(BT\_RST\_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(BT\_WAKE\_AP\_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(AP\_WAKE\_NFC\_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(NFC\_EN\_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(NFC\_INT\_PI1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(GPS\_EN\_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(GPS\_RST\_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(UART4\_TX\_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(UART4\_RX\_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(UART4\_RTS\_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(UART4\_CTS\_PI7, UARTD, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(GEN1\_I2C\_SDA\_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), PINCFG(GEN1\_I2C\_SCL\_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), PINCFG(GEN2\_I2C\_SCL\_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), PINCFG(GEN2\_I2C\_SDA\_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), PINCFG(DAP4\_FS\_PJ4, I2S4B, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(DAP4\_DIN\_PJ5, I2S4B, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(DAP4\_DOUT\_PJ6, I2S4B, DOWN, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(DAP4\_SCLK\_PJ7, I2S4B, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(SDMMC1\_CLK\_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC1\_CMD\_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC1\_DAT3\_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC1\_DAT2\_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC1\_DAT1\_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC1\_DAT0\_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC3\_CLK\_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC3\_CMD\_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC3\_DAT3\_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC3\_DAT2\_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC3\_DAT1\_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC3\_DAT0\_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(CAM1\_MCLK\_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(CAM2\_MCLK\_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(CAM\_I2C\_SCL\_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH), PINCFG(CAM\_I2C\_SDA\_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH), PINCFG(CAM\_RST\_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(CAM\_AF\_EN\_PS5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(CAM\_FLASH\_EN\_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(CAM1\_PWDN\_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(CAM2\_PWDN\_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(CAM1\_STROBE\_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(UART1\_TX\_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(UART1\_RX\_PU1, UARTA, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(UART1\_RTS\_PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(UART1\_CTS\_PU3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(LCD\_BL\_PWM\_PV0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(LCD\_BL\_EN\_PV1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(LCD\_RST\_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(LCD\_GPIO1\_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(LCD\_GPIO2\_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(AP\_READY\_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(TOUCH\_RST\_PV6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(TOUCH\_CLK\_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(MODEM\_WAKE\_AP\_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(TOUCH\_INT\_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(MOTION\_INT\_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(ALS\_PROX\_INT\_PX3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(TEMP\_ALERT\_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(BUTTON\_POWER\_ON\_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(BUTTON\_VOL\_UP\_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(BUTTON\_VOL\_DOWN\_PX7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(BUTTON\_SLIDE\_SW\_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(BUTTON\_HOME\_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(LCD\_TE\_PY2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(PWR\_I2C\_SCL\_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), PINCFG(PWR\_I2C\_SDA\_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), PINCFG(CLK\_32K\_OUT\_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(PZ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(DAP2\_FS\_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(DAP2\_SCLK\_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(DAP2\_DIN\_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(DAP2\_DOUT\_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(AUD\_MCLK\_PBB0, AUD, UP, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(DVFS\_PWM\_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(DVFS\_CLK\_PBB2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(GPIO\_X1\_AUD\_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(GPIO\_X3\_AUD\_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(HDMI\_CEC\_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), PINCFG(HDMI\_INT\_DP\_HPD\_PCC1, DP, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), PINCFG(SPDIF\_OUT\_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(SPDIF\_IN\_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(USB\_VBUS\_EN0\_PCC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL), PINCFG(USB\_VBUS\_EN1\_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), PINCFG(DP\_HPD0\_PCC6, DP, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), PINCFG(SPI2\_CS1\_PDD0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(QSPI\_SCK\_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(QSPI\_CS\_N\_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(QSPI\_IO0\_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(QSPI\_IO1\_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(QSPI\_IO2\_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(QSPI\_IO3\_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(CORE\_PWR\_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(CPU\_PWR\_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PWR\_INT\_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(CLK\_32K\_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(JTAG\_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(CLK\_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), }; #define DRVCFG(\_drvgrp, \_slwf, \_slwr, \_drvup, \_drvdn, \_lpmd, \_schmt, _hsm) { .drvgrp = PMUX\_DRVGRP_##\_drvgrp, .slwf = \_slwf, .slwr = \_slwr, .drvup = \_drvup, .drvdn = _drvdn, .lpmd = PMUX\_LPMD_##_lpmd, .schmt = PMUX\_SCHMT_##_schmt, .hsm = PMUX\_HSM_##\_hsm, } static const struct pmux\_drvgrp\_config p3450\_porg\_drvgrps = { }; #endif /\* PINMUX\_CONFIG\_P3450\_PORG\_H \*/ ---
**Author:** ![BARO](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/baro/32/82443_2.png) [@BARO](https://forums.developer.nvidia.com/u/BARO)\ **Post date:** [October 8, 2019, 12:17pm UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/10 "2019-10-08T12:17:16Z")
> [@](#): > > Deaar Jon, > I have modified pinmux-config-p3450-porg.h as per direction, now I2S sound is working fine. > > Regards, > > Yashwant Hi Did you modify only the h file without the files dtsi ? or you made all the process explained in the documentation to do it? Because i have the screen with the NVIDIA logo after to made all the procedure to update the pinmux. ---
**Author:** ![yas\_its](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@yas\_its](https://forums.developer.nvidia.com/u/yas_its)\ **Post date:** [October 8, 2019, 1:16pm UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/11 "2019-10-08T13:16:47Z")
Sound will work only after updating of .h file. for flushing the u-boot.bin, use following. > **[GitHub - gtjoseph/jetson-nano-support at l4t\_32.2.1](https://github.com/gtjoseph/jetson-nano-support/tree/l4t_32.2.1)** > > Contribute to gtjoseph/jetson-nano-support development by creating an account on GitHub. ---
**Author:** ![officeqm793](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@officeqm793](https://forums.developer.nvidia.com/u/officeqm793)\ **Post date:** [October 2, 2020, 10:19pm UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/12 "2020-10-02T22:19:20Z")
Hello Jon, Is this issue ever been solved/fixed? I would like you to post a new documentation how to do this correctly at your earliest is possible. Thank you, Laszlo ---
**Author:** ![maverich](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@maverich](https://forums.developer.nvidia.com/u/maverich)\ **Post date:** [November 18, 2020, 10:49am UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/13 "2020-11-18T10:49:27Z")
link expired :/ is this issue resolved? ---
**Author:** ![jonathanh](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jonathanh/32/14043_2.png) [@jonathanh](https://forums.developer.nvidia.com/u/jonathanh)\ **Post date:** [November 18, 2020, 11:05am UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/14 "2020-11-18T11:05:26Z")
Hello! If you are using the SD-card version of the Jetson Nano devkit and not the eMMC version, then you can use the jetson-io tool to configure the I2S signals … ```auto $ sudo /opt/nvidia/jetson-io/config-by-function.py -o dtb i2s4 $ sudo reboot ``` For more details on jetson-io please see this [doc](https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%2520Linux%2520Driver%2520Package%2520Development%2520Guide%2Fhw_setup_jetson_io.html%23). The application note is no longer necessary because it has been superseded by this tool. Regards Jon ---
**Author:** ![nadeemm](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/nadeemm/32/367020_2.png) [@nadeemm](https://forums.developer.nvidia.com/u/nadeemm)\ **Post date:** [October 14, 2021, 9:59pm UTC](https://forums.developer.nvidia.com/t/i2s-sound-in-jetpack4-2-2-l4t-r32-2-1/82675/15 "2021-10-14T21:59:36Z")