merwin
October 13, 2022, 9:30pm
1
In our design we have the Jetson Nano I2S1 connected as a master to an audio codec. When we output 48KHz audio the I2S1_CLK should be 3.072MHz but it is only 1.536MHz. The I2S1_FS is correct at 48KHz.
I’ve tried to change the bclk-ratio for dai-link-2 in the dts but it had no effect.
kayccc
October 14, 2022, 12:07am
2
merwin
October 14, 2022, 5:29pm
3
None of the troubleshooting tips helped.
I am actually not making any changes to the device tree since all the defaults should be correct for our codec.
There are not many examples of using dai-link-2 (I2S1) so I may be missing something specifically for it. The pin muxing and GPIO setup looks correct and the mixer is setup with the following command for the /dev/snd/pcmC1D1p device:
amixer sset -c tegrasndt210ref 'I2S3 Mux' 'ADMAIF2'
Hi Merwin,
May I know, what is the Jetpack release version used for your development?.
One quick suggestion to try out on BCLK ratio, The I2Sx used for your codec exposes mixer control “BCLK Ratio” can you try setting this control to value “2”
merwin
October 24, 2022, 12:09pm
7
We are using JetPack 4.5 (L4T 32.5).
Setting the “BCLK Ratio” mixer control does not make any difference either.
Hi Merwin,
Thanks for the Jetpack info.
Can you provide the clock tree summary during the audio playback with BCLK Ratio setting to 2.
cat /sys/kernel/debug/clk/clk_summary
merwin
October 28, 2022, 8:08pm
10
# cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate req_rate accuracy phase
----------------------------------------------------------------------------------------------------------------------
dfllCPU_out 1 1 1479000000 1479000000 0 0
*[ default_freq 0]
cclk_g 1 1 1479000000 0 0 0
*[ default_freq 0]
32khz_out0 0 0 32768 32768 0 0
*[ default_freq 0]
sil9396-mclk 0 0 12288000 12288000 0 0
*[ default_freq 0]
vimclk_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
i2s4_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
i2s3_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
i2s2_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
i2s1_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
i2s0_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
dmic3_sync_clk_mux 0 0 24576000 0 0 0
*[ default_freq 0]
dmic3_sync_clk 0 0 24576000 0 0 0
*[ default_freq 0]
dmic2_sync_clk_mux 0 0 24576000 0 0 0
*[ default_freq 0]
dmic2_sync_clk 0 0 24576000 0 0 0
*[ default_freq 0]
dmic1_sync_clk_mux 0 0 24576000 0 0 0
*[ default_freq 0]
dmic1_sync_clk 0 0 24576000 0 0 0
*[ default_freq 0]
spdif_in_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
spdif_mux 0 0 24576000 0 0 0
*[ default_freq 0]
spdif 0 0 24576000 0 0 0
*[ default_freq 0]
spdif_doubler 0 0 49152000 0 0 0
*[ default_freq 0]
spdif_div 0 0 49152000 0 0 0
*[ default_freq 0]
spdif_2x 0 0 49152000 0 0 0
*[ default_freq 0]
audio4_mux 0 0 24576000 0 0 0
*[ default_freq 0]
audio4 0 0 24576000 0 0 0
*[ default_freq 0]
audio3_mux 0 0 24576000 0 0 0
*[ default_freq 0]
audio3 0 0 24576000 0 0 0
*[ default_freq 0]
audio2_mux 0 0 24576000 0 0 0
*[ default_freq 0]
audio2 0 0 24576000 0 0 0
*[ default_freq 0]
audio1_mux 0 0 24576000 0 0 0
*[ default_freq 0]
audio1 0 0 24576000 0 0 0
*[ default_freq 0]
audio0_mux 0 0 24576000 0 0 0
*[ default_freq 0]
audio0 0 0 24576000 0 0 0
*[ default_freq 0]
pd2vi 0 0 0 0 0 0
*[ default_freq 0]
sor1_brick 1 1 297000000 297000000 0 0
*[ default_freq 0]
sor1 1 1 297000000 0 0 0
*[ default_freq 0]
clk_32k 1 1 32768 32768 0 0
*[ default_freq 0]
blink_override 0 0 32768 32768 0 0
*[ default_freq 0]
blink 0 0 32768 32768 0 0
*[ default_freq 0]
rtc 1 1 32768 32768 0 0
*[ default_freq 0]
osc 4 4 38400000 38400000 0 0
*[ default_freq 0]
clk_out_2_mux 0 0 38400000 38400000 0 0
*[ default_freq 0]
clk_out_2 0 0 38400000 38400000 0 0
*[ default_freq 0]
usb2_hsic_trk 0 0 9600000 9600000 0 0
*[ default_freq 0]
hsic_trk 0 0 9600000 0 0 0
*[ default_freq 0]
usb2_trk 0 0 9600000 0 0 0
*[ default_freq 0]
xusb_gate 1 1 38400000 38400000 0 0
*[ default_freq 0]
pll_mb 0 0 806400000 806400000 0 0
*[ default_freq 0]
pll_mb_ud 0 0 806400000 806400000 0 0
*[ default_freq 0]
pll_m 1 1 1600000000 1600000000 0 0
*[ default_freq 0]
pll_m_ud 1 1 1600000000 1600000000 0 0
*[ default_freq 0]
emc 3 3 1600000000 0 0 0
emc_master 2 2 1600000000 1600000000 0 0
bwmgr.emc 1 1 1600000000 1600000000 0 0
override.emc 1 1 1600000000 1600000000 0 0
mc 4 4 400000000 0 0 0
*[ default_freq 0]
mc_cdpa 1 1 400000000 51000000 0 0
*[ default_freq 0]
mc_ccpa 1 1 400000000 51000000 0 0
*[ default_freq 0]
mc_cbpa 1 1 400000000 51000000 0 0
*[ default_freq 0]
mc_capa 1 1 400000000 51000000 0 0
*[ default_freq 0]
pll_ref 11 11 38400000 38400000 0 0
*[ default_freq 0]
pll_x 0 0 1017600000 1017600000 0 0
*[ default_freq 0]
pll_x_out0 0 0 508800000 508800000 0 0
*[ default_freq 0]
pll_a1 0 0 307200000 307200000 0 0
*[ default_freq 0]
aclk 0 0 307200000 19200000 0 0
*[ default_freq 0]
adsp_neon 0 0 307200000 19200000 0 0
*[ default_freq 0]
adsp 0 0 307200000 19200000 0 0
*[ default_freq 0]
abus 0 0 307200000 307200000 0 0
override.abus 0 0 307200000 307200000 0 0
cap.vcore.abus 0 0 844800000 4294967295 0 0
adsp.cpu.abus 0 0 307200000 307200000 0 0
pll_a 2 2 368639843 368640000 0 0
*[ default_freq 0]
pll_a_out0_div 1 1 49151980 61440000 0 0
*[ default_freq 0]
pll_a_out0 3 3 49151980 49152000 0 0
*[ default_freq 0]
i2s4 0 0 49151980 11289600 0 0
*[ default_freq 0]
i2s3 0 0 6553598 1536000 0 0
*[ default_freq 0]
i2s2 1 1 1536000 1536000 0 0
*[ default_freq 0]
i2s1 0 0 49151980 11289600 0 0
*[ default_freq 0]
i2s0 0 0 49151980 11289600 0 0
*[ default_freq 0]
extern1 3 3 12287995 12288000 0 0
*[ default_freq 0]
clk_out_1_mux 2 2 12287995 38400000 0 0
*[ default_freq 0]
clk_out_1 1 1 12287995 38400000 0 0
*[ default_freq 0]
dmic1 0 0 12287995 3072000 0 0
*[ default_freq 0]
dmic2 0 0 12287995 3072000 0 0
*[ default_freq 0]
dmic3 0 0 49151980 0 0 0
*[ default_freq 0]
pll_a_out_adsp 0 0 368639843 0 0 0
*[ default_freq 0]
pll_a_out0_out_adsp 0 0 368639843 0 0 0
*[ default_freq 0]
pllg_ref 2 2 38400000 38400000 0 0
*[ default_freq 0]
gpcclk 1 1 921600000 921600000 0 0
*[ default_freq 0]
gbus 1 1 921600000 921600000 0 0
floor.profile_gbus 0 0 921600000 0 0 0
floor.gbus 0 0 921600000 0 0 0
override.gbus 0 0 921600000 0 0 0
cap.profile_gbus 0 0 1300000000 1300000000 0 0
cap.throttle_gbus 0 0 1300000000 1300000000 0 0
cap.vgpu.gbus 0 0 1300000000 1300000000 0 0
edp.gbus 0 0 1300000000 1300000000 0 0
cap.gbus 0 0 1300000000 1300000000 0 0
gm20b.gbus 1 1 921600000 921600000 0 0
gpu 1 1 38400000 38400000 0 0
*[ default_freq 0]
pll_p 27 32 408000000 408000000 0 0
*[ default_freq 0]
d_audio 2 2 81600000 81600000 0 0
*[ default_freq 0]
sbc1 1 1 16000000 16000000 0 0
*[ default_freq 0]
pwm 1 1 48000000 48000000 0 0
*[ default_freq 0]
vii2c 2 2 81600000 83200000 0 0
*[ default_freq 0]
cilab 1 1 102000000 102000000 0 0
*[ default_freq 0]
cilcd 1 1 102000000 102000000 0 0
*[ default_freq 0]
cile 1 1 102000000 102000000 0 0
*[ default_freq 0]
extern3 1 1 48000000 24000000 0 0
*[ default_freq 0]
clk_out_3_mux 1 1 48000000 38400000 0 0
*[ default_freq 0]
clk_out_3 1 1 48000000 48000000 0 0
*[ default_freq 0]
clk72mhz 2 2 68000000 68000000 0 0
*[ default_freq 0]
mipi-cal 1 1 68000000 408000000 0 0
*[ default_freq 0]
sata_oob 0 0 204000000 204000000 0 0
*[ default_freq 0]
sata 0 0 102000000 104000000 0 0
*[ default_freq 0]
dfll_ref 2 2 51000000 51000000 0 0
*[ default_freq 0]
dfll_soc 2 2 51000000 51000000 0 0
*[ default_freq 0]
sclk_mux 2 2 408000000 204000000 0 0
*[ default_freq 0]
sclk 2 2 136000000 136000000 0 0
*[ default_freq 0]
sclk_skipper 2 2 102000000 102000000 0 0
*[ default_freq 0]
sbus 1 1 102000000 102000000 0 0
vcm.sclk 0 0 102000000 204000000 0 0
cap.vcore.sclk 0 0 408000000 4294967295 0 0
camera.sclk 0 0 102000000 204000000 0 0
mon.avp 0 0 102000000 204000000 0 0
wake.sclk 0 0 102000000 204000000 0 0
bsea.sclk 0 0 102000000 204000000 0 0
avp.sclk 0 0 102000000 204000000 0 0
override.sclk 0 0 102000000 204000000 0 0
floor.sclk 0 0 102000000 204000000 0 0
cap.throttle.sclk 0 0 408000000 408000000 0 0
cap.sclk 0 0 408000000 408000000 0 0
ahb.sclk 1 1 102000000 51000000 0 0
vcm.ahb.sclk 0 0 102000000 204000000 0 0
sdmmc4.sclk 0 0 102000000 204000000 0 0
usb2.sclk 0 0 102000000 204000000 0 0
usb1.sclk 0 0 102000000 204000000 0 0
usbd.sclk 0 0 102000000 204000000 0 0
apb.sclk 1 1 51000000 51000000 0 0
wifi.sclk 0 0 51000000 102000000 0 0
vcm.apb.sclk 0 0 51000000 102000000 0 0
boot.apb.sclk 1 1 51000000 51000000 0 0
qspi.sclk 0 0 51000000 102000000 0 0
sbc4.sclk 0 0 51000000 102000000 0 0
sbc3.sclk 0 0 51000000 102000000 0 0
sbc2.sclk 0 0 51000000 102000000 0 0
sbc1.sclk 0 0 51000000 102000000 0 0
hclk_div 1 1 102000000 204000000 0 0
*[ default_freq 0]
hclk 1 1 102000000 24000000 0 0
*[ default_freq 0]
pclk_div 1 1 51000000 102000000 0 0
*[ default_freq 0]
pclk 2 2 51000000 12000000 0 0
*[ default_freq 0]
cec 1 1 51000000 0 0 0
*[ default_freq 0]
uartd 0 0 408000000 408000000 0 0
*[ default_freq 0]
uartc 1 1 153586 153600 0 0
*[ default_freq 0]
uartb 0 0 408000000 408000000 0 0
*[ default_freq 0]
hda 2 2 51000000 51000000 0 0
*[ default_freq 0]
hda2codec_2x 2 2 48000000 48000000 0 0
*[ default_freq 0]
ape 3 3 25500000 25500000 0 0
*[ default_freq 0]
ape_master 0 0 25500000 204000000 0 0
override.ape 0 0 25500000 204000000 0 0
xbar.ape 0 0 25500000 204000000 0 0
adsp.ape 0 0 25500000 204000000 0 0
adma.ape 0 0 25500000 204000000 0 0
sdmmc2 0 0 204000000 204000000 0 0
*[ default_freq 0]
pll_p_out_adsp 0 0 408000000 408000000 0 0
*[ default_freq 0]
pll_p_out_cpu 0 0 408000000 408000000 0 0
*[ default_freq 0]
pll_p_out4_div 0 0 102000000 0 0 0
*[ default_freq 0]
pll_p_out4 0 0 102000000 102000000 0 0
*[ default_freq 0]
dpaux1 0 0 408000000 408000000 0 0
*[ default_freq 0]
uarta 1 1 408000000 408000000 0 0
*[ default_freq 0]
csite 1 1 136000000 136000000 0 0
*[ default_freq 0]
vi_sensor 0 0 408000000 408000000 0 0
*[ default_freq 0]
soc_therm 1 1 51000000 51000000 0 0
*[ default_freq 0]
sbc4 1 1 12000000 12000000 0 0
*[ default_freq 0]
sbc3 0 0 408000000 408000000 0 0
*[ default_freq 0]
vi_sensor2 0 0 408000000 408000000 0 0
*[ default_freq 0]
sdmmc3 0 0 3175098 100000 0 0
*[ default_freq 0]
sdmmc1 0 0 204000000 204000000 0 0
*[ default_freq 0]
spdif_in 0 0 408000000 408000000 0 0
*[ default_freq 0]
mselect 2 2 408000000 408000000 0 0
*[ default_freq 0]
mselect_master 0 0 408000000 102000000 0 0
override.mselect 0 0 408000000 102000000 0 0
pcie.mselect 0 0 408000000 102000000 0 0
cpu.mselect 0 0 408000000 102000000 0 0
afi 1 1 408000000 102000000 0 0
*[ default_freq 0]
host1x 2 2 81600000 136000000 0 0
*[ default_freq 0]
host1x_master 1 1 81600000 81000000 0 0
override.host1x 0 0 81600000 163200000 0 0
floor.host1x 0 0 81600000 163200000 0 0
cap.vcore.host1x 0 0 408000000 4294967295 0 0
cap.host1x 0 0 408000000 408000000 0 0
vii2c.host1x 0 0 81600000 163200000 0 0
vi.host1x 0 0 81600000 163200000 0 0
nv.host1x 2 2 81600000 81000000 0 0
i2c6 0 1 81600000 83200000 0 0
*[ default_freq 0]
i2c5 1 2 136000000 136000000 0 0
*[ default_freq 0]
i2c4 0 1 20400000 20800000 0 0
*[ default_freq 0]
i2c3 0 1 81600000 83200000 0 0
*[ default_freq 0]
i2c2 0 1 20400000 20800000 0 0
*[ default_freq 0]
i2c1 0 1 81600000 83200000 0 0
*[ default_freq 0]
pll_p_out_hsio 0 0 408000000 408000000 0 0
*[ default_freq 0]
pll_p_out_xusb 0 0 408000000 408000000 0 0
*[ default_freq 0]
xusb_dev_src 0 0 102000000 102000000 0 0
*[ default_freq 0]
xusb_dev 0 0 102000000 19200000 0 0
*[ default_freq 0]
xusb_host_src 0 0 102000000 102000000 0 0
*[ default_freq 0]
xusb_host 0 0 102000000 19200000 0 0
*[ default_freq 0]
pll_p_out5_div 1 1 204000000 408000000 0 0
*[ default_freq 0]
pll_p_out5 1 1 204000000 204000000 0 0
*[ default_freq 0]
pll_p_out3_div 1 1 102000000 408000000 0 0
*[ default_freq 0]
pll_p_out3 1 1 102000000 102000000 0 0
*[ default_freq 0]
csi 1 1 102000000 408000000 0 0
*[ default_freq 0]
sdmmc_legacy 0 0 12000000 12000000 0 0
*[ default_freq 0]
pll_p_out1_div 0 0 408000000 408000000 0 0
*[ default_freq 0]
pll_p_out1 0 0 408000000 408000000 0 0
*[ default_freq 0]
pll_p_out2 0 0 204000000 0 0 0
*[ default_freq 0]
pll_p_ud 0 0 408000000 0 0 0
*[ default_freq 0]
sor_safe 2 2 24000000 0 0 0
*[ default_freq 0]
pll_d2 1 1 297000000 25173906 0 0
*[ default_freq 0]
pll_d2_out0 1 1 297000000 297000000 0 0
*[ default_freq 0]
disp1 1 1 297000000 25173906 0 0
*[ default_freq 0]
sor1_mux 0 0 297000000 25173906 0 0
*[ default_freq 0]
pll_dp 2 2 270000000 270000000 0 0
*[ default_freq 0]
sor0 1 1 270000000 0 0 0
*[ default_freq 0]
pll_c4_vco 0 0 998400000 998400000 0 0
*[ default_freq 0]
pll_c4_out2 0 0 199680000 134400000 0 0
*[ default_freq 0]
sdmmc4 0 0 199680000 200000000 0 0
*[ default_freq 0]
pll_c4_out1 0 0 332800000 224000000 0 0
*[ default_freq 0]
pll_c4_out0 0 0 998400000 0 0 0
*[ default_freq 0]
pll_c4_out3_div 0 0 998400000 672000000 0 0
*[ default_freq 0]
pll_c4_out3 0 0 998400000 672000000 0 0
*[ default_freq 0]
pll_e 1 1 100000000 100000000 0 0
*[ default_freq 0]
cml1 0 0 100000000 100000000 0 0
*[ default_freq 0]
cml0 0 0 100000000 100000000 0 0
*[ default_freq 0]
pll_re_vco 2 2 672000000 672000000 0 0
*[ default_freq 0]
pll_re_out1_div 0 0 672000000 624000000 0 0
*[ default_freq 0]
pll_re_out1 0 0 672000000 624000000 0 0
*[ default_freq 0]
pll_re_out 0 0 672000000 624000000 0 0
*[ default_freq 0]
xusb_falcon_src 0 0 336000000 336000000 0 0
*[ default_freq 0]
pll_d 1 1 594000000 326400000 0 0
*[ default_freq 0]
pll_d_out0 1 1 297000000 297000000 0 0
*[ default_freq 0]
disp2 1 1 297000000 25175000 0 0
*[ default_freq 0]
pll_d_dsi_out 0 0 297000000 163200000 0 0
*[ default_freq 0]
dsib 0 0 297000000 163200000 0 0
*[ default_freq 0]
dsia 0 0 297000000 163200000 0 0
*[ default_freq 0]
pll_u_vco 1 1 480000000 480000000 0 0
*[ default_freq 0]
pll_u_480M 0 0 480000000 480000000 0 0
*[ default_freq 0]
xusb_ss_src 0 0 120000000 120000000 0 0
*[ default_freq 0]
xusb_ss 0 0 120000000 19200000 0 0
*[ default_freq 0]
xusb_ssp_src 0 0 120000000 19200000 0 0
*[ default_freq 0]
xusb_hs_src 0 0 120000000 19200000 0 0
*[ default_freq 0]
xusb_ss_div2 0 0 60000000 0 0 0
*[ default_freq 0]
pll_u_out 2 2 240000000 240000000 0 0
*[ default_freq 0]
pll_u_out2_div 1 1 60000000 240000000 0 0
*[ default_freq 0]
pll_u_out2 1 1 60000000 60000000 0 0
*[ default_freq 0]
pll_u_60M 0 0 60000000 240000000 0 0
*[ default_freq 0]
pll_u_out1_div 1 1 48000000 240000000 0 0
*[ default_freq 0]
pll_u_out1 1 1 48000000 48000000 0 0
*[ default_freq 0]
pll_u_48M 0 0 48000000 240000000 0 0
*[ default_freq 0]
xusb_fs_src 0 0 48000000 19200000 0 0
*[ default_freq 0]
pll_c3 0 0 268800000 268800000 0 0
*[ default_freq 0]
nvdec 0 0 268800000 716800000 0 0
*[ default_freq 0]
nvenc 0 0 268800000 408000000 0 0
*[ default_freq 0]
c3bus 0 0 268800000 0 0 0
cap.vcore.c3bus 0 0 1200000000 4294967295 0 0
floor.c3bus 0 0 268800000 307200000 0 0
override.c3bus 0 0 268800000 307200000 0 0
cap.throttle.c3bus 0 0 1200000000 1200000000 0 0
cap.c3bus 0 0 1200000000 1200000000 0 0
nvdec.cbus 0 0 268800000 788480000 0 0
nvenc.cbus 0 0 268800000 1200000000 0 0
pll_c2 0 0 192000000 192000000 0 0
*[ default_freq 0]
vic03 0 0 192000000 192000000 0 0
*[ default_freq 0]
se 0 0 192000000 524800000 0 0
*[ default_freq 0]
tsecb 0 0 192000000 192000000 0 0
*[ default_freq 0]
nvjpg 0 0 192000000 408000000 0 0
*[ default_freq 0]
c2bus 0 0 192000000 0 0 0
vic.floor.cbus 0 0 192000000 0 0 0
cap.vcore.c2bus 0 0 1200000000 4294967295 0 0
edp.c2bus 0 0 1200000000 1200000000 0 0
override.c2bus 0 0 192000000 307200000 0 0
floor.c2bus 0 0 192000000 307200000 0 0
cap.throttle.c2bus 0 0 1200000000 1200000000 0 0
cap.c2bus 0 0 1200000000 1200000000 0 0
tsecb.cbus 0 0 192000000 1200000000 0 0
se.cbus 0 0 192000000 510000000 0 0
nvjpg.cbus 0 0 192000000 1200000000 0 0
vic03.cbus 0 0 192000000 140800000 0 0
pll_c 2 2 793600000 793600000 0 0
*[ default_freq 0]
vi 2 2 793600000 793600000 0 0
*[ default_freq 0]
vi_output 0 0 793600000 0 0 0
*[ default_freq 0]
isp 0 0 793600000 408000000 0 0
*[ default_freq 0]
ispb 0 0 793600000 19200000 0 0
*[ default_freq 0]
ispa 0 0 793600000 19200000 0 0
*[ default_freq 0]
cbus 1 1 793600000 793600000 0 0
override.cbus 0 0 793600000 307200000 0 0
isp.cbus 0 0 793600000 307200000 0 0
ispb.isp.cbus 0 0 793600000 1200000000 0 0
ispa.isp.cbus 0 0 793600000 1200000000 0 0
vi.cbus 1 1 793600000 307200000 0 0
vi_bypass.cbus 0 0 793600000 307200000 0 0
vi_v4l2.cbus 1 1 793600000 4294967295 0 0
pll_c_ud 0 0 793600000 307200000 0 0
*[ default_freq 0]
pll_c_out1_div 0 0 793600000 307200000 0 0
*[ default_freq 0]
pll_c_out1 0 0 793600000 307200000 0 0
*[ default_freq 0]
clk_m 13 13 19200000 19200000 0 0
*[ default_freq 0]
sbc2 0 0 984616 1000000 0 0
*[ default_freq 0]
tsensor 1 1 400000 400000 0 0
*[ default_freq 0]
cclk_lp 0 0 19200000 19200000 0 0
*[ default_freq 0]
iqc2 0 0 19200000 19200000 0 0
*[ default_freq 0]
iqc1 0 0 19200000 19200000 0 0
*[ default_freq 0]
apb2ape 1 1 19200000 19200000 0 0
*[ default_freq 0]
dpaux 1 1 19200000 19200000 0 0
*[ default_freq 0]
pcie 1 1 19200000 19200000 0 0
*[ default_freq 0]
vim2_clk 0 0 19200000 19200000 0 0
*[ default_freq 0]
dtv 0 0 19200000 19200000 0 0
*[ default_freq 0]
dp2 0 0 19200000 19200000 0 0
*[ default_freq 0]
csus 0 0 19200000 19200000 0 0
*[ default_freq 0]
usb2 0 0 19200000 19200000 0 0
*[ default_freq 0]
usbd 0 0 19200000 19200000 0 0
*[ default_freq 0]
bsev 0 0 19200000 19200000 0 0
*[ default_freq 0]
hda2hdmi 2 2 19200000 19200000 0 0
*[ default_freq 0]
kfuse 1 1 19200000 19200000 0 0
*[ default_freq 0]
fuse_burn 0 0 19200000 19200000 0 0
*[ default_freq 0]
fuse 5 5 19200000 19200000 0 0
*[ default_freq 0]
apbdma 1 1 19200000 19200000 0 0
*[ default_freq 0]
timer 3 3 19200000 19200000 0 0
*[ default_freq 0]
maud 0 0 19200000 19200000 0 0
*[ default_freq 0]
uartape 0 0 9600000 9600000 0 0
*[ default_freq 0]
mipibif 0 0 19200000 19200000 0 0
*[ default_freq 0]
qspi 0 0 19200000 19200000 0 0
*[ default_freq 0]
qspi_out 0 0 19200000 19200000 0 0
*[ default_freq 0]
dbgapb 1 1 19200000 19200000 0 0
*[ default_freq 0]
entropy 1 1 19200000 19200000 0 0
*[ default_freq 0]
extern2 0 0 19200000 19200000 0 0
*[ default_freq 0]
i2cslow 1 1 984616 1000000 0 0
*[ default_freq 0]
actmon 3 3 19200000 19200000 0 0
*[ default_freq 0]
dsiblp 0 0 19200000 19200000 0 0
*[ default_freq 0]
dsialp 0 0 19200000 19200000 0 0
*[ default_freq 0]
owr 0 0 19200000 19200000 0 0
*[ default_freq 0]
la 0 0 19200000 19200000 0 0
*[ default_freq 0]
spdif_out 0 0 19200000 19200000 0 0
*[ default_freq 0]
tsec 0 0 19200000 19200000 0 0
*[ default_freq 0]
clk_m_div4 0 0 4800000 4800000 0 0
*[ default_freq 0]
clk_m_div2 0 0 9600000 9600000 0 0
*[ default_freq 0]
mkumard
October 31, 2022, 5:03am
11
Merwin,
From the log, the clock summary shows the requested I2S clock was 1.536 MHz which was exactly provided by clock module. So the request from driver itself seems to be 1.536MHz. Can you add some debug logs in the I2S driver hw_params function call to print the info on Fs, bps, channels, bclk value and i2sclock rate before requesting the clock set function.
system
Closed
November 23, 2022, 3:59am
13
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