I2s1_sync_clk is not setting and placed wrong

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

I tried to ALC5633 I2S porting however I2S signal and data is not work so i searched what happen.

HW is ok cuz other old TX2 kernel is works well but my Jetpack 4.4 is not work . and i found something wrong.

sudo cat /sys/kernel/debug/clk/clk_summary

why i2s1_sync_clk is under spdifin_sync_input ? and i2s1_sync_input is setting wrong clk?

i using default clock setting and

i want to set i2s1_sync_clk but i cant find how to set.

thx

*[        default_freq                                       0]
 i2s6_sync_input                                            0            0           0           0          0 0
 *[        default_freq                                       0]
 i2s5_sync_input                                            0            0           0           0          0 0
 *[        default_freq                                       0]
 i2s4_sync_input                                            0            0           0           0          0 0
 *[        default_freq                                       0]
 i2s3_sync_input                                            0            0           0           0          0 0
 *[        default_freq                                       0]
 i2s2_sync_input                                            0            0           0           0          0 0
 *[        default_freq                                       0]           0     1411200     1411200          0 0
 i2s1_sync_input                                            0            0     1411200     1411200          0 0
 *[        default_freq                                       0] 
      dspk2_sync_clk                                          0            0     1411200           0          0 0
    *[        default_freq                                       0]
    dspk1_sync_clk                                          0            0     1411200           0          0 0
    *[        default_freq                                       0]
    dmic4_sync_clk                                          0            0     1411200           0          0 0
    *[        default_freq                                       0]
    dmic3_sync_clk                                          0            0     1411200           0          0 0
    *[        default_freq                                       0]
    dmic2_sync_clk                                          0            0     1411200           0          0 0
    *[        default_freq                                       0]
    dmic1_sync_clk                                          0            0     1411200           0          0 0
    *[        default_freq                                       0]
 spdifin_sync_input                                         0            0           0           0          0 0
 *[        default_freq                                       0]
    i2s6_sync_clk                                           0            0           0           0          0 0
    *[        default_freq                                       0]
    i2s5_sync_clk                                           0            0           0           0          0 0
    *[        default_freq                                       0]
    i2s4_sync_clk                                           0            0           0           0          0 0
    *[        default_freq                                       0]
    i2s3_sync_clk                                           0            0           0           0          0 0
    *[        default_freq                                       0]
    i2s2_sync_clk                                           0            0           0           0          0 0
    *[        default_freq                                       0]
    i2s1_sync_clk                                           0            0           0           0          0 0
    *[        default_freq                                       0]

....

i followed these threads
https://forums.developer.nvidia.com/t/audio-codec-rt5631-on-tx2/59379/4

https://forums.developer.nvidia.com/t/audio-codec-rt5631-on-tx2-jetpack-4-4/179418
3

i tested older version . (not my source )

sound is work well but Jetpack is 3.x version

i2s clk is works well and i2s1 clk setting use default… what is diffrent?

why i2s2_sync_input~ 6 and dspk2_sync_clk is sperated and placed weird ?
i2s1_sync_input 0 0 1411200 1411200 0 0
*[ default_freq 0]
i2s1_sync_clk 0 0 1411200 0 0 0
*[ default_freq 0]
dspk2_sync_clk 0 0 1411200 0 0 0
*[ default_freq 0]
dspk1_sync_clk 0 0 1411200 0 0 0
*[ default_freq 0]
dmic4_sync_clk 0 0 1411200 0 0 0
*[ default_freq 0]
dmic3_sync_clk 0 0 1411200 0 0 0
*[ default_freq 0]
dmic2_sync_clk 0 0 1411200 0 0 0
*[ default_freq 0]
dmic1_sync_clk 0 0 1411200 0 0 0
*[ default_freq 0]
spdifin_sync_input 0 0 0 0 0 0
*[ default_freq 0]
spdif_sync_clk 0 0 0 0 0 0
*[ default_freq 0]
i2s6_sync_clk 0 0 0 0 0 0
*[ default_freq 0]
i2s5_sync_clk 0 0 0 0 0 0
*[ default_freq 0]
i2s4_sync_clk 0 0 0 0 0 0
*[ default_freq 0]
i2s3_sync_clk 0 0 0 0 0 0

4

Hi, May I know why and how do you want to use i2s1_sync_clk in your usecase. For normal I2S playback/capture usecase, you should just check i2s1 clock.

I wonder if you have done Pinmux settings (for audio pins) correctly as per the BSP document. Can you re-confirm that?

Thanks,
Sharad

5

i update Jetpack 4.4. version for another reason and i testedJetpack 3.x version using same board.
old version sound works well.st I2S0_SDIN, I2S0_SOUT, I2S0_CLK, I2S0_LRCLK, MCLK waves is changed.
but new version is not.

i wanna find to different points and i found i2s1_sync_clk is different.

	tegra_i2s1: i2s@2901000 {
		compatible = "nvidia,tegra210-i2s";
		reg = <0x0 0x2901000 0x0 0x100>;
		nvidia,ahub-i2s-id = <0>;
		clocks = <&tegra_car TEGRA186_CLK_I2S1>,
			 <&tegra_car TEGRA186_CLK_PLL_A_OUT0>,
			 <&tegra_car TEGRA186_CLK_I2S1_SYNC_INPUT>,
			 <&tegra_car TEGRA186_CLK_SYNC_I2S1>,
			 <&tegra_car TEGRA186_CLK_I2S1_SYNC_INPUT>;
		clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
			      "audio_sync", "clk_sync_input";

		assigned-clocks = <&tegra_car TEGRA186_CLK_I2S1>;
		assigned-clock-parents =
			<&tegra_car TEGRA186_CLK_PLL_A_OUT0>;
		assigned-clock-rates = <1536000>;
		pinctrl-names = "dap_active", "dap_inactive";
		pinctrl-0 = <>;
		pinctrl-1 = <>;
		fsync-width = <31>;
		/* status = "disabled"; */
		status = "okay"; 
	};

i think that TEGRA186_CLK_SYNC_I2S1 is under CLK_I2S1_SYNC_INPUT.
but JP 4.4 , TEGRA186_CLK_SYNC_I2S1 is under the “spdifin_sync_input”.
even i removed sound card driver codes TEGRA186_CLK_SYNC_I2S1 is not changed

6

Bank: 0 Reg: 0x02431028 Val: 0x00000055 → dap1_fs_pj3
Bank: 0 Reg: 0x02431030 Val: 0x00000055 → dap1_din_pj2
Bank: 0 Reg: 0x02431038 Val: 0x00000055 → dap1_dout_pj1
Bank: 0 Reg: 0x02431040 Val: 0x00000055 → dap1_sclk_pj0

i think that pin mux is not setted

7

i reconfigure pinmux setting and saw i2s data is coming but audio still not work so need a more steps

8

+++ b/kernel/nvidia/sound/soc/tegra-alt/include/tegra210_i2s_alt.h
@@ -200,6 +200,10 @@ enum tegra210_i2s_path {
struct tegra210_i2s {
struct clk *clk_i2s;
struct clk *clk_sync_input;
+#if 1
+ struct clk *clk_audio_sync;
+#endif
struct regmap *regmap;
const char *prod_name;
struct regulator_bulk_data *supplies;

+++ b/kernel/nvidia/sound/soc/tegra-alt/tegra210_i2s_alt.c
@@ -84,13 +86,27 @@ static int tegra210_i2s_set_clock_rate(struct device *dev, int clock_rate)
dev_err(dev, “Can’t set I2S clock rate: %d\n”, ret);
return ret;
}
+#if 1
+ ret = clk_set_parent(i2s->clk_audio_sync, i2s->clk_sync_input);
+ if (ret) {
+ dev_err(dev, “Can’t set parent of I2S clock\n”);
+ return ret;
+ }
+#endif

added clk and

i2s1_sync_input 0 0 1536000 1536000 0 0
[ default_freq 0]
i2s1_sync_clk 0 0 1536000 0 0 0
[ default_freq 0]
dspk2_sync_clk 0 0 1536000 0 0 0
[ default_freq 0]
dspk1_sync_clk 0 0 1536000 0 0 0
[ default_freq 0]
…
i2s1_sync_clk was set but audio still not work orz…

9

Hi, How did you confirm if the i2s data is coming? Did you probe I2S1 data and clock Signals?
As I told in my earlier post, you don’t need to worry about i2s1_sync_clk for normal playback over codec.

Are you using AUD_MCLK in your design, please set pinmux for that as well?

Thanks,
Sharad

10

Screenshot from 2021-06-07 14-35-33

i watched AUD_MCLK, I2S0 pins by scope. mclk is 12.x Mhz now and will change to 9.6mhz

i have never seen i2s so it could be wrong. so you are right and i think that not incoming i2s data problem caused by pinmux setting not i2s1_sync_clk.

11

finally sound is working and reason was pinmux default setting is changed 3.x version and 4.4.

THX sharadg !!

Tip : my custom board need a 9.6 mhz aud_mclk clk but default is 12.2 mhz
if someone wanna changing aud_mclk, fix DT under clk_m not pll_a_out0 .

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