Hello. These days I’m developing a camera kernel driver for TX2. In fact I do not know about TX2. The ISP model name is ov491 and mipi data is output immediately when connected. I built a kernel driver and a device tree based on the information given by nvidia, and only the green screen is displayed. Can you give me a guide on what to do?
[ 161.041879] [OV491]: streaming start.
[ 161.045593] [OV491]: streaming check.
[ 162.608296] fence timeout on [ffffffc0690e5400] after 1500ms
[ 162.609446] fence timeout on [ffffffc0690e5200] after 1500ms
[ 162.609457] fence timeout on [ffffffc1a5da4000] after 1500ms
[ 162.609467] name=[nvhost_sync:25], current value=0 waiting value=1
[ 162.609476] name=[nvhost_sync:37], current value=0 waiting value=1
[ 162.609479] ---- mlocks ----
[ 162.609485] ---- mlocks ----
[ 162.609499] 8: locked by channel 6
[ 162.609503] 8: locked by channel 6
[ 162.609527] ---- syncpts ----
[ 162.609530] ---- syncpts ----
[ 162.609552] id 4 (disp_d) min 117 max 117 refs 1 (previous client : )
[ 162.609565] id 5 (disp_e) min 2 max 2 refs 1 (previous client : )
[ 162.609577] id 7 (vblank1) min 9488 max 0 refs 1 (previous client : )
[ 162.609603] id 18 (17000000.gp10b_507) min 8592 max 8592 refs 1 (previous client : )
[ 162.609614] id 19 (17000000.gp10b_506) min 22 max 22 refs 1 (previous client : )
[ 162.609627] id 21 (17000000.gp10b_505) min 624 max 624 refs 1 (previous client : 17000000.gp10b_505)
[ 162.609636] id 22 (15600000.isp_nvcamera-daemon_0) min 0 max 4 refs 4 (previous client : )
[ 162.609645] id 23 (15600000.isp_nvcamera-daemon_1) min 0 max 2 refs 4 (previous client : )
[ 162.609655] id 24 (15600000.isp_nvcamera-daemon_2) min 0 max 2 refs 4 (previous client : )
[ 162.609663] id 25 (15600000.isp_nvcamera-daemon_3) min 0 max 2 refs 4 (previous client : )
[ 162.609675] id 28 (15600000.isp_nvcamera-daemon_4) min 15 max 26 refs 9 (previous client : )
[ 162.609684] id 29 (15600000.isp_nvcamera-daemon_5) min 0 max 2 refs 4 (previous client : )
[ 162.609695] id 31 (17000000.gp10b_503) min 10 max 10 refs 1 (previous client : )
[ 162.609710] id 35 (15700000.vi_0) min 14 max 14 refs 2 (previous client : 15700000.vi_0)
[ 162.609719] id 36 (15700000.vi_0) min 1 max 2 refs 4 (previous client : 15700000.vi_0)
[ 162.609729] id 37 (15700000.vi_1) min 0 max 2 refs 4 (previous client : 15700000.vi_1)
[ 162.609738] id 38 (15700000.vi_2) min 0 max 2 refs 4 (previous client : 15700000.vi_2)
[ 162.609748] id 39 (150c0000.nvcsi_0) min 36 max 36 refs 2 (previous client : 150c0000.nvcsi_0)
[ 162.609767] id 47 (17000000.gp10b_494) min 8 max 8 refs 1 (previous client : )
[ 162.609777] id 48 (17000000.gp10b_493) min 6 max 6 refs 1 (previous client : )
[ 162.609785] id 49 (17000000.gp10b_492) min 6 max 6 refs 1 (previous client : )
[ 162.609794] id 50 (17000000.gp10b_491) min 6 max 6 refs 1 (previous client : )
[ 162.609803] id 51 (17000000.gp10b_490) min 6 max 6 refs 1 (previous client : )
[ 162.609812] id 52 (17000000.gp10b_489) min 6 max 6 refs 1 (previous client : )
[ 162.610547] ---- channels ----
[ 162.610561] id 4 (disp_d) min 117 max 117 refs 1 (previous client : )
[ 162.610573] id 5 (disp_e) min 2 max 2 refs 1 (previous client : )
[ 162.610575]
channel 1 - 15820000.se
[ 162.610581] NvHost basic channel registers:
[ 162.610585] id 7 (vblank1) min 9488 max 0 refs 1 (previous client : )
[ 162.610588] CMDFIFO_STAT_0: 00002040
[ 162.610595] CMDFIFO_RDATA_0: 88a0b010
[ 162.610604] CMDP_OFFSET_0: 00000000
[ 162.610609] CMDP_CLASS_0: 00000000
[ 162.610612] id 18 (17000000.gp10b_507) min 8592 max 8592 refs 1 (previous client : )
[ 162.610615] CHANNELSTAT_0: 00000000
[ 162.610620] The CDMA sync queue is empty.
[ 162.610624] id 19 (17000000.gp10b_506) min 22 max 22 refs 1 (previous client : )
[ 162.610636]
channel 2 - 15830000.se
[ 162.610639] id 21 (17000000.gp10b_505) min 624 max 624 refs 1 (previous client : 17000000.gp10b_505)
[ 162.610641] NvHost basic channel registers:
[ 162.610647] CMDFIFO_STAT_0: 00002040
[ 162.610650] id 22 (15600000.isp_nvcamera-daemon_0) min 0 max 4 refs 4 (previous client : )
[ 162.610654] CMDFIFO_RDATA_0: 0102412c
[ 162.610660] id 23 (15600000.isp_nvcamera-daemon_1) min 0 max 2 refs 4 (previous client : )
[ 162.610662] CMDP_OFFSET_0: 00000000
[ 162.610668] CMDP_CLASS_0: 00000000
[ 162.610671] id 24 (15600000.isp_nvcamera-daemon_2) min 0 max 2 refs 4 (previous client : )
[ 162.610673] CHANNELSTAT_0: 00000000
[ 162.610677] The CDMA sync queue is empty.
[ 162.610680] id 25 (15600000.isp_nvcamera-daemon_3) min 0 max 2 refs 4 (previous client : )
[ 162.610691]
channel 3 - 15840000.se
[ 162.610694] id 28 (15600000.isp_nvcamera-daemon_4) min 15 max 26 refs 9 (previous client : )
[ 162.610697] NvHost basic channel registers:
[ 162.610702] CMDFIFO_STAT_0: 00002040
[ 162.610705] id 29 (15600000.isp_nvcamera-daemon_5) min 0 max 2 refs 4 (previous client : )
[ 162.610708] CMDFIFO_RDATA_0: 04851a79
[ 162.610716] id 31 (17000000.gp10b_503) min 10 max 10 refs 1 (previous client : )
[ 162.610718] CMDP_OFFSET_0: 00000000
[ 162.610724] CMDP_CLASS_0: 00000000
[ 162.610729] CHANNELSTAT_0: 00000000
[ 162.610731] id 35 (15700000.vi_0) min 14 max 14 refs 2 (previous client : 15700000.vi_0)
[ 162.610734] The CDMA sync queue is empty.
[ 162.610741] id 36 (15700000.vi_0) min 1 max 2 refs 4 (previous client : 15700000.vi_0)
[ 162.610744]
channel 6 - 15600000.isp
[ 162.610748] NvHost basic channel registers:
[ 162.610751] id 37 (15700000.vi_1) min 0 max 2 refs 4 (previous client : 15700000.vi_1)
[ 162.610754] CMDFIFO_STAT_0: 00004000
[ 162.610760] id 38 (15700000.vi_2) min 0 max 2 refs 4 (previous client : 15700000.vi_2)
[ 162.610762] CMDFIFO_RDATA_0: 004e0041
[ 162.610770] id 39 (150c0000.nvcsi_0) min 36 max 36 refs 2 (previous client : 150c0000.nvcsi_0)
[ 162.610772] CMDP_OFFSET_0: 00000050
[ 162.610778] CMDP_CLASS_0: 00000001
[ 162.610782] CHANNELSTAT_0: 00000000
[ 162.610789] id 47 (17000000.gp10b_494) min 8 max 8 refs 1 (previous client : )
[ 162.610797]
ffffffc07b21ee00: JOB, syncpt_id=22, syncpt_val=2, first_get=000001f8, timeout=10000, num_slots=19
[ 162.610799] id 48 (17000000.gp10b_493) min 6 max 6 refs 1 (previous client : )
[ 162.610809] id 49 (17000000.gp10b_492) min 6 max 6 refs 1 (previous client : )
[ 162.610818] id 50 (17000000.gp10b_491) min 6 max 6 refs 1 (previous client : )
[ 162.610821] GATHER at 5a708000+3bec, 12 words
[ 162.610830] 20000001
[ 162.610831] id 51 (17000000.gp10b_490) min 6 max 6 refs 1 (previous client : )
[ 162.610841] 00006416 20000001
[ 162.610842] id 52 (17000000.gp10b_489) min 6 max 6 refs 1 (previous client : )
[ 162.610872] 00006817 20000001 00006c18 20000001 00007c19 20000001 0000741d 200c0001 00000005
[ 162.610884] GATHER at 5a708000+3c1c, 2 words
[ 162.610896] 20000001 0000001c
[ 162.610908]
channel 5 - 150c0000.nvcsi
[ 162.610913] NvHost basic channel registers:
[ 162.610918] CMDFIFO_STAT_0: 00002040
[ 162.610924] CMDFIFO_RDATA_0: 00000027
[ 162.610931] CMDP_OFFSET_0: 00000000
[ 162.610936] CMDP_CLASS_0: 00000001
[ 162.610941] CHANNELSTAT_0: 00000000
[ 162.610945] The CDMA sync queue is empty.
[ 162.610956]
channel 0 - 15700000.vi
[ 162.610960] NvHost basic channel registers:
[ 162.610965] CMDFIFO_STAT_0: 00002040
[ 162.610970] CMDFIFO_RDATA_0: 00000023
[ 162.610977] CMDP_OFFSET_0: 00000000
[ 162.610982] CMDP_CLASS_0: 00000001
[ 162.610987] CHANNELSTAT_0: 00000000
[ 162.610991] The CDMA sync queue is empty.
[ 162.610999]
channel 4 - 15700000.vi
[ 162.611002] NvHost basic channel registers:
[ 162.611007] CMDFIFO_STAT_0: 0000001b
[ 162.611012] CMDFIFO_RDATA_0: 304e0005
[ 162.611019] CMDP_OFFSET_0: 00000050
[ 162.611024] CMDP_CLASS_0: 00000001
[ 162.611029] CHANNELSTAT_0: 00000000
[ 162.611042]
ffffffc1cb3e3000: JOB, syncpt_id=38, syncpt_val=1, first_get=00000000, timeout=0, num_slots=7
[ 162.611057] GATHER at 5a718000+0000, 6 words
[ 162.611081] 304e0005 0000000f 0000001c 304e0005 00000000 00000026
[ 162.611089] GATHER at 5a718000+0018, 29 words
[ 162.611184] 90000002 a0004008 00013f1f 00000aff 9000000c a000400c 00000720 000003ac 00000001 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000720 000003ac 90000002 a0004018 007f0000 00000104 90000002 a0004021 00000000 00000000 90000001 a0004045 0003d5ea
[ 162.611192] GATHER at 5a718000+008c, 26 words
[ 162.611275] 90000001 a0000401 00000000 90000001 a000404d 00000001 90000001 a0004020 00000000 90000003 a0004042 5a526000 00000000 00000001 90000001 a0004048 00000000 90000001 a000400a 00000000 90000001 a0004001 00000001 90000001 a0004007 00000003
[ 162.611283] GATHER at 5a718000+00f4, 2 words
[ 162.611293] 20000001 00000024
[ 162.611304]
---- host general irq ----
[ 162.611311] sync_intc0mask = 0x00000001
[ 162.611317] sync_intmask = 0x50000003
[ 162.611320]
---- host syncpt irq mask ----
[ 162.611324]
---- host syncpt irq status ----
[ 162.611332] syncpt_thresh_cpu0_int_status(0) = 0x00000000
[ 162.611339] syncpt_thresh_cpu0_int_status(1) = 0x00000000
[ 162.611345] syncpt_thresh_cpu0_int_status(2) = 0x00000000
[ 162.611352] syncpt_thresh_cpu0_int_status(3) = 0x00000000
[ 162.611357] syncpt_thresh_cpu0_int_status(4) = 0x00000000
[ 162.611363] syncpt_thresh_cpu0_int_status(5) = 0x00000000
[ 162.611369] syncpt_thresh_cpu0_int_status(6) = 0x00000000
[ 162.611375] syncpt_thresh_cpu0_int_status(7) = 0x00000000
[ 162.611381] syncpt_thresh_cpu0_int_status(8) = 0x00000000
[ 162.611387] syncpt_thresh_cpu0_int_status(9) = 0x00000000
[ 162.611393] syncpt_thresh_cpu0_int_status(10) = 0x00000000
[ 162.611399] syncpt_thresh_cpu0_int_status(11) = 0x00000000
[ 162.611405] syncpt_thresh_cpu0_int_status(12) = 0x00000000
[ 162.611411] syncpt_thresh_cpu0_int_status(13) = 0x00000000
[ 162.611417] syncpt_thresh_cpu0_int_status(14) = 0x00000000
[ 162.611423] syncpt_thresh_cpu0_int_status(15) = 0x00000000
[ 162.611429] syncpt_thresh_cpu0_int_status(16) = 0x00000000
[ 162.611435] syncpt_thresh_cpu0_int_status(17) = 0x00000000
[ 162.611562] ---- channels ----
[ 162.611571]
channel 1 - 15820000.se
[ 162.611573] NvHost basic channel registers:
[ 162.611576] CMDFIFO_STAT_0: 00002040
[ 162.611579] CMDFIFO_RDATA_0: 88a0b010
[ 162.611584] CMDP_OFFSET_0: 00000000
[ 162.611586] CMDP_CLASS_0: 00000000
[ 162.611589] CHANNELSTAT_0: 00000000
[ 162.611591] The CDMA sync queue is empty.
[ 162.611595]
channel 2 - 15830000.se
[ 162.611597] NvHost basic channel registers:
[ 162.611599] CMDFIFO_STAT_0: 00002040
[ 162.611602] CMDFIFO_RDATA_0: 0102412c
[ 162.611606] CMDP_OFFSET_0: 00000000
[ 162.611608] CMDP_CLASS_0: 00000000
[ 162.611611] CHANNELSTAT_0: 00000000
[ 162.611612] The CDMA sync queue is empty.
[ 162.611616]
channel 3 - 15840000.se
[ 162.611618] NvHost basic channel registers:
[ 162.611620] CMDFIFO_STAT_0: 00002040
[ 162.611623] CMDFIFO_RDATA_0: 04851a79
[ 162.611627] CMDP_OFFSET_0: 00000000
[ 162.611629] CMDP_CLASS_0: 00000000
[ 162.611632] CHANNELSTAT_0: 00000000
[ 162.611633] The CDMA sync queue is empty.
[ 162.611637]
channel 6 - 15600000.isp
[ 162.611638] NvHost basic channel registers:
[ 162.611640] CMDFIFO_STAT_0: 00004000
[ 162.611643] CMDFIFO_RDATA_0: 004e0041
[ 162.611647] CMDP_OFFSET_0: 00000050
[ 162.611650] CMDP_CLASS_0: 00000001
[ 162.611652] CHANNELSTAT_0: 00000000
[ 162.611658]
ffffffc07b21ee00: JOB, syncpt_id=22, syncpt_val=2, first_get=000001f8, timeout=10000, num_slots=19
[ 162.611662] GATHER at 5a708000+3bec, 12 words
[ 162.611680] 20000001 00006416 20000001 00006817 20000001 00006c18 20000001 00007c19 20000001 0000741d 200c0001 00000005
[ 162.611683] GATHER at 5a708000+3c1c, 2 words
[ 162.611688] 20000001 0000001c
[ 162.611692]
channel 5 - 150c0000.nvcsi
[ 162.611694] NvHost basic channel registers:
[ 162.611696] CMDFIFO_STAT_0: 00002040
[ 162.611699] CMDFIFO_RDATA_0: 00000027
[ 162.611703] CMDP_OFFSET_0: 00000000
[ 162.611705] CMDP_CLASS_0: 00000001
[ 162.611708] CHANNELSTAT_0: 00000000
[ 162.611709] The CDMA sync queue is empty.
[ 162.611713]
channel 0 - 15700000.vi
[ 162.611714] NvHost basic channel registers:
[ 162.611717] CMDFIFO_STAT_0: 00002040
[ 162.611719] CMDFIFO_RDATA_0: 00000023
[ 162.611723] CMDP_OFFSET_0: 00000000
[ 162.611725] CMDP_CLASS_0: 00000001
[ 162.611728] CHANNELSTAT_0: 00000000
[ 162.611729] The CDMA sync queue is empty.
[ 162.611732]
channel 4 - 15700000.vi
[ 162.611733] NvHost basic channel registers:
[ 162.611736] CMDFIFO_STAT_0: 0000001b
[ 162.611738] CMDFIFO_RDATA_0: 304e0005
[ 162.611742] CMDP_OFFSET_0: 00000050
[ 162.611745] CMDP_CLASS_0: 00000001
[ 162.611747] CHANNELSTAT_0: 00000000
[ 162.611752]
ffffffc1cb3e3000: JOB, syncpt_id=38, syncpt_val=1, first_get=00000000, timeout=0, num_slots=7
[ 162.611755] GATHER at 5a718000+0000, 6 words
[ 162.611764] 304e0005 0000000f 0000001c 304e0005 00000000 00000026
[ 162.611767] GATHER at 5a718000+0018, 29 words
[ 162.611804] 90000002 a0004008 00013f1f 00000aff 9000000c a000400c 00000720 000003ac 00000001 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000720 000003ac 90000002 a0004018 007f0000 00000104 90000002 a0004021 00000000 00000000 90000001 a0004045 0003d5ea
[ 162.611807] GATHER at 5a718000+008c, 26 words
[ 162.611839] 90000001 a0000401 00000000 90000001 a000404d 00000001 90000001 a0004020 00000000 90000003 a0004042 5a526000 00000000 00000001 90000001 a0004048 00000000 90000001 a000400a 00000000 90000001 a0004001 00000001 90000001 a0004007 00000003
[ 162.611842] GATHER at 5a718000+00f4, 2 words
[ 162.611845] 20000001 00000024
[ 162.611849]
---- host general irq ----
[ 162.611852] sync_intc0mask = 0x00000001
[ 162.611855] sync_intmask = 0x50000003
[ 162.611856]
---- host syncpt irq mask ----
[ 162.611857]
---- host syncpt irq status ----
[ 162.611861] syncpt_thresh_cpu0_int_status(0) = 0x00000000
[ 162.611864] syncpt_thresh_cpu0_int_status(1) = 0x00000000
[ 162.611867] syncpt_thresh_cpu0_int_status(2) = 0x00000000
[ 162.611869] syncpt_thresh_cpu0_int_status(3) = 0x00000000
[ 162.611872] syncpt_thresh_cpu0_int_status(4) = 0x00000000
[ 162.611875] syncpt_thresh_cpu0_int_status(5) = 0x00000000
[ 162.611878] syncpt_thresh_cpu0_int_status(6) = 0x00000000
[ 162.611880] syncpt_thresh_cpu0_int_status(7) = 0x00000000
[ 162.611883] syncpt_thresh_cpu0_int_status(8) = 0x00000000
[ 162.611886] syncpt_thresh_cpu0_int_status(9) = 0x00000000
[ 162.611889] syncpt_thresh_cpu0_int_status(10) = 0x00000000
[ 162.611891] syncpt_thresh_cpu0_int_status(11) = 0x00000000
[ 162.611894] syncpt_thresh_cpu0_int_status(12) = 0x00000000
[ 162.611897] syncpt_thresh_cpu0_int_status(13) = 0x00000000
[ 162.611900] syncpt_thresh_cpu0_int_status(14) = 0x00000000
[ 162.611902] syncpt_thresh_cpu0_int_status(15) = 0x00000000
[ 162.611905] syncpt_thresh_cpu0_int_status(16) = 0x00000000
[ 162.611908] syncpt_thresh_cpu0_int_status(17) = 0x00000000
[ 163.999534] name=[nvhost_sync:22], current value=0 waiting value=1
[ 164.005769] ---- mlocks ----
[ 164.008697] 8: locked by channel 6
[ 164.013664] ---- syncpts ----
[ 164.016666] id 4 (disp_d) min 117 max 117 refs 1 (previous client : )
[ 164.023154] id 5 (disp_e) min 86 max 87 refs 1 (previous client : )
[ 164.029464] id 7 (vblank1) min 9574 max 0 refs 1 (previous client : )
[ 164.035971] id 18 (17000000.gp10b_507) min 8592 max 8592 refs 1 (previous client : )
[ 164.043739] id 19 (17000000.gp10b_506) min 22 max 22 refs 1 (previous client : )
[ 164.051143] id 21 (17000000.gp10b_505) min 624 max 624 refs 1 (previous client : 17000000.gp10b_505)
[ 164.060274] id 22 (15600000.isp_nvcamera-daemon_0) min 0 max 4 refs 4 (previous client : )
[ 164.068545] id 23 (15600000.isp_nvcamera-daemon_1) min 0 max 2 refs 4 (previous client : )
[ 164.076817] id 24 (15600000.isp_nvcamera-daemon_2) min 0 max 2 refs 4 (previous client : )
[ 164.085307] id 25 (15600000.isp_nvcamera-daemon_3) min 0 max 2 refs 4 (previous client : )
[ 164.094046] id 28 (15600000.isp_nvcamera-daemon_4) min 15 max 26 refs 9 (previous client : )
[ 164.102630] id 29 (15600000.isp_nvcamera-daemon_5) min 0 max 2 refs 4 (previous client : )
[ 164.111045] id 31 (17000000.gp10b_503) min 10 max 10 refs 1 (previous client : )
[ 164.118584] id 35 (15700000.vi_0) min 14 max 14 refs 2 (previous client : 15700000.vi_0)
[ 164.126733] id 36 (15700000.vi_0) min 1 max 2 refs 4 (previous client : 15700000.vi_0)
[ 164.134752] id 37 (15700000.vi_1) min 0 max 2 refs 4 (previous client : 15700000.vi_1)
[ 164.142736] id 38 (15700000.vi_2) min 0 max 2 refs 4 (previous client : 15700000.vi_2)
[ 164.150803] id 39 (150c0000.nvcsi_0) min 36 max 36 refs 2 (previous client : 150c0000.nvcsi_0)
[ 164.159509] id 47 (17000000.gp10b_494) min 8 max 8 refs 1 (previous client : )
[ 164.166854] id 48 (17000000.gp10b_493) min 6 max 6 refs 1 (previous client : )
[ 164.174147] id 49 (17000000.gp10b_492) min 6 max 6 refs 1 (previous client : )
[ 164.181468] id 50 (17000000.gp10b_491) min 6 max 6 refs 1 (previous client : )
[ 164.188756] id 51 (17000000.gp10b_490) min 6 max 6 refs 1 (previous client : )
[ 164.196045] id 52 (17000000.gp10b_489) min 6 max 6 refs 1 (previous client : )
[ 164.205522] ---- channels ----
[ 164.208667]
channel 1 - 15820000.se
[ 164.215216] NvHost basic channel registers:
[ 164.219481] CMDFIFO_STAT_0: 00002040
[ 164.223196] CMDFIFO_RDATA_0: 88a0b010
[ 164.226930] CMDP_OFFSET_0: 00000000
[ 164.230629] CMDP_CLASS_0: 00000000
[ 164.234315] CHANNELSTAT_0: 00000000
[ 164.238007] The CDMA sync queue is empty.
[ 164.243562]
channel 2 - 15830000.se
[ 164.250033] NvHost basic channel registers:
[ 164.254239] CMDFIFO_STAT_0: 00002040
[ 164.257940] CMDFIFO_RDATA_0: 0102412c
[ 164.261629] CMDP_OFFSET_0: 00000000
[ 164.265324] CMDP_CLASS_0: 00000000
[ 164.269009] CHANNELSTAT_0: 00000000
[ 164.272704] The CDMA sync queue is empty.
[ 164.278234]
channel 3 - 15840000.se
[ 164.284705] NvHost basic channel registers:
[ 164.288910] CMDFIFO_STAT_0: 00002040
[ 164.292601] CMDFIFO_RDATA_0: 04851a79
[ 164.296282] CMDP_OFFSET_0: 00000000
[ 164.299941] CMDP_CLASS_0: 00000000
[ 164.303632] CHANNELSTAT_0: 00000000
[ 164.307321] The CDMA sync queue is empty.
[ 164.312900]
channel 6 - 15600000.isp
[ 164.319461] NvHost basic channel registers:
[ 164.323706] CMDFIFO_STAT_0: 00004000
[ 164.327401] CMDFIFO_RDATA_0: 004e0041
[ 164.331093] CMDP_OFFSET_0: 00000050
[ 164.334782] CMDP_CLASS_0: 00000001
[ 164.338468] CHANNELSTAT_0: 00000000
[ 164.342159]
ffffffc07b21ee00: JOB, syncpt_id=22, syncpt_val=2, first_get=000001f8, timeout=10000, num_slots=19
[ 164.353658] GATHER at 5a708000+3bec, 12 words
[ 164.358383] 20000001 00006416 20000001 00006817 20000001 00006c18 20000001 00007c19 20000001 0000741d 200c0001 00000005
[ 164.369446] GATHER at 5a708000+3c1c, 2 words
[ 164.374081] 20000001 0000001c
[ 164.378693]
channel 5 - 150c0000.nvcsi
[ 164.385414] NvHost basic channel registers:
[ 164.389626] CMDFIFO_STAT_0: 00002040
[ 164.393313] CMDFIFO_RDATA_0: 00000027
[ 164.397003] CMDP_OFFSET_0: 00000000
[ 164.400688] CMDP_CLASS_0: 00000001
[ 164.404389] CHANNELSTAT_0: 00000000
[ 164.408049] The CDMA sync queue is empty.
[ 164.413615]
channel 0 - 15700000.vi
[ 164.420079] NvHost basic channel registers:
[ 164.424289] CMDFIFO_STAT_0: 00002040
[ 164.427946] CMDFIFO_RDATA_0: 00000023
[ 164.431638] CMDP_OFFSET_0: 00000000
[ 164.435327] CMDP_CLASS_0: 00000001
[ 164.439021] CHANNELSTAT_0: 00000000
[ 164.442705] The CDMA sync queue is empty.
[ 164.448253]
channel 4 - 15700000.vi
[ 164.454714] NvHost basic channel registers:
[ 164.458930] CMDFIFO_STAT_0: 0000001b
[ 164.462613] CMDFIFO_RDATA_0: 304e0005
[ 164.466310] CMDP_OFFSET_0: 00000050
[ 164.469998] CMDP_CLASS_0: 00000001
[ 164.473695] CHANNELSTAT_0: 00000000
[ 164.477386]
ffffffc1cb3e3000: JOB, syncpt_id=38, syncpt_val=1, first_get=00000000, timeout=0, num_slots=7
[ 164.488455] GATHER at 5a718000+0000, 6 words
[ 164.493093] 304e0005 0000000f 0000001c 304e0005 00000000 00000026
[ 164.499364] GATHER at 5a718000+0018, 29 words
[ 164.504087] 90000002 a0004008 00013f1f 00000aff 9000000c a000400c 00000720 000003ac 00000001 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000720 000003ac 90000002 a0004018 007f0000 00000104 90000002 a0004021 00000000 00000000 90000001 a0004045 0003d5ea
[ 164.528665] GATHER at 5a718000+008c, 26 words
[ 164.533389] 90000001 a0000401 00000000 90000001 a000404d 00000001 90000001 a0004020 00000000 90000003 a0004042 5a526000 00000000 00000001 90000001 a0004048 00000000 90000001 a000400a 00000000 90000001 a0004001 00000001 90000001 a0004007 00000003
[ 164.555581] GATHER at 5a718000+00f4, 2 words
[ 164.560249] 20000001 00000024
[ 164.564846]
---- host general irq ----
[ 164.571578] sync_intc0mask = 0x00000001
[ 164.575442] sync_intmask = 0x50000003
[ 164.579155]
---- host syncpt irq mask ----
[ 164.586246]
---- host syncpt irq status ----
[ 164.593502] syncpt_thresh_cpu0_int_status(0) = 0x00000000
[ 164.598925] syncpt_thresh_cpu0_int_status(1) = 0x00000000
[ 164.604346] syncpt_thresh_cpu0_int_status(2) = 0x00000000
[ 164.609764] syncpt_thresh_cpu0_int_status(3) = 0x00000000
[ 164.615186] syncpt_thresh_cpu0_int_status(4) = 0x00000000
[ 164.620611] syncpt_thresh_cpu0_int_status(5) = 0x00000000
[ 164.626044] syncpt_thresh_cpu0_int_status(6) = 0x00000000
[ 164.631467] syncpt_thresh_cpu0_int_status(7) = 0x00000000
[ 164.636889] syncpt_thresh_cpu0_int_status(8) = 0x00000000
[ 164.642310] syncpt_thresh_cpu0_int_status(9) = 0x00000000
[ 164.647730] syncpt_thresh_cpu0_int_status(10) = 0x00000000
[ 164.653238] syncpt_thresh_cpu0_int_status(11) = 0x00000000
[ 164.658743] syncpt_thresh_cpu0_int_status(12) = 0x00000000
[ 164.664260] syncpt_thresh_cpu0_int_status(13) = 0x00000000
[ 164.669767] syncpt_thresh_cpu0_int_status(14) = 0x00000000
[ 164.675280] syncpt_thresh_cpu0_int_status(15) = 0x00000000
[ 164.680794] syncpt_thresh_cpu0_int_status(16) = 0x00000000
[ 164.686314] syncpt_thresh_cpu0_int_status(17) = 0x00000000
[ 167.108388] host1x 13e10000.host1x: CaptureSchedule: syncpoint id 28 (15600000.isp_nvcamera-daemon_4) stuck waiting 18, timeout=-1
[ 167.120217] ---- syncpts ----
[ 167.123623] id 4 (disp_d) min 117 max 117 refs 1 (previous client : )
[ 167.130190] id 5 (disp_e) min 272 max 273 refs 1 (previous client : )
[ 167.136927] id 7 (vblank1) min 9760 max 0 refs 1 (previous client : )
[ 167.143555] id 18 (17000000.gp10b_507) min 8592 max 8592 refs 1 (previous client : )
[ 167.151398] id 19 (17000000.gp10b_506) min 22 max 22 refs 1 (previous client : )
[ 167.159111] id 21 (17000000.gp10b_505) min 624 max 624 refs 1 (previous client : 17000000.gp10b_505)
[ 167.168363] id 22 (15600000.isp_nvcamera-daemon_0) min 0 max 4 refs 4 (previous client : )
[ 167.176725] id 23 (15600000.isp_nvcamera-daemon_1) min 0 max 2 refs 4 (previous client : )
[ 167.185067] id 24 (15600000.isp_nvcamera-daemon_2) min 0 max 2 refs 4 (previous client : )
[ 167.193389] id 25 (15600000.isp_nvcamera-daemon_3) min 0 max 2 refs 4 (previous client : )
[ 167.201728] id 28 (15600000.isp_nvcamera-daemon_4) min 15 max 26 refs 9 (previous client : )
[ 167.210380] id 29 (15600000.isp_nvcamera-daemon_5) min 0 max 2 refs 4 (previous client : )
[ 167.218896] id 31 (17000000.gp10b_503) min 10 max 10 refs 1 (previous client : )
[ 167.226411] id 35 (15700000.vi_0) min 14 max 14 refs 2 (previous client : 15700000.vi_0)
[ 167.234560] id 36 (15700000.vi_0) min 1 max 2 refs 4 (previous client : 15700000.vi_0)
[ 167.242499] id 37 (15700000.vi_1) min 0 max 2 refs 4 (previous client : 15700000.vi_1)
[ 167.250567] id 38 (15700000.vi_2) min 0 max 2 refs 4 (previous client : 15700000.vi_2)
[ 167.258585] id 39 (150c0000.nvcsi_0) min 36 max 36 refs 2 (previous client : 150c0000.nvcsi_0)
[ 167.267238] id 47 (17000000.gp10b_494) min 8 max 8 refs 1 (previous client : )
[ 167.274484] id 48 (17000000.gp10b_493) min 6 max 6 refs 1 (previous client : )
[ 167.281731] id 49 (17000000.gp10b_492) min 6 max 6 refs 1 (previous client : )
[ 167.288973] id 50 (17000000.gp10b_491) min 6 max 6 refs 1 (previous client : )
[ 167.296221] id 51 (17000000.gp10b_490) min 6 max 6 refs 1 (previous client : )
[ 167.303459] id 52 (17000000.gp10b_489) min 6 max 6 refs 1 (previous client : )
this my dmsg
hello withmarine,
according to your failure logs,
there is sync point timeout failure.
[ 162.608296] fence timeout on [ffffffc0690e5400] after 1500ms
[ 162.609446] fence timeout on [ffffffc0690e5200] after 1500ms
[ 162.609457] fence timeout on [ffffffc1a5da4000] after 1500ms
...
[ 162.610797]
ffffffc07b21ee00: JOB, syncpt_id=22, syncpt_val=2, first_get=000001f8, timeout=10000, num_slots=19
in generally, this is tegra device cannot receive mipi signaling correctly.
some suggestions as below,
- please review the regulator settings.
- please review your device tree properties, they should following your sensor specification.
- please also co-work with your hardware engineer to measure the mipi signaling.
jerryChang Thank you for your reply.
First of all, can you review my device tree and kernel souce?
I then modified the device tree to pixel_t = “uyvy”;
Then the command to output video stops and does not operate.
my command :
gst-launch-1.0 nvcamerasrc sensor-id=0 ! 'video/x-raw(memory:NVMM),width=1824, height=940, framerate=30/1, format=NV16' ! nvoverlaysink -ev
my device tree :
/*
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/ {
host1x {
vi@15700000 {
num-channels = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3327_vi_in0: endpoint {
csi-port = <2>;
bus-width = <2>;
remote-endpoint = <&e3327_csi_out0>;
};
};
};
};
nvcsi@150c0000 {
num-channels = <1>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3327_csi_in0: endpoint@0 {
csi-port = <2>;
bus-width = <2>;
remote-endpoint = <&e3327_ov491_out0>;
};
};
port@1 {
reg = <1>;
e3327_csi_out0: endpoint@1 {
remote-endpoint = <&e3327_vi_in0>;
};
};
};
};
};
};
i2c@3180000 {
ov491_a@24 {
compatible = "nvidia,ov491";
/* I2C device address */
reg = <0x24>;
/* V4L2 device node location */
devnode = "video0";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
avdd-reg = "vana";
iovdd-reg = "vif";
/* Sensor output flip settings */
vertical-flip = "true";
/**
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* mclk_khz = "";
* Standard MIPI driving clock, typically 24MHz
*
* num_lanes = "";
* Number of lane channels sensor is programmed to output
*
* tegra_sinterface = "";
* The base tegra serial interface lanes are connected to
*
* discontinuous_clk = "";
* The sensor is programmed to use a discontinuous clock on MIPI lanes
*
* dpcm_enable = "true";
* The sensor is programmed to use a DPCM modes
*
* cil_settletime = "";
* MIPI lane settle time value.
* A "0" value attempts to autocalibrate based on mclk_multiplier
*
*
*
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* line_length = "";
* Pixel line length (width) for sensor mode.
* This is used to calibrate features in our camera stack.
*
* mclk_multiplier = "";
* Multiplier to MCLK to help time hardware capture sequence
* TODO: Assign to PLL_Multiplier as well until fixed in core
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
*
*
*
*
* inherent_gain = "";
* Gain obtained inherently from mode (ie. pixel binning)
*
* min_gain_val = ""; (floor to 6 decimal places)
* max_gain_val = ""; (floor to 6 decimal places)
* Gain limits for mode
*
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (us)
*
*
* min_hdr_ratio = "";
* max_hdr_ratio = "";
* HDR Ratio limits for mode
*
* min_framerate = "";
* max_framerate = "";
* Framerate limits for mode (fps)
*/
mode0 { //OV5693_MODE_1824x940
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_a";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1824";
active_h = "940";
pixel_t = "uyvy";
readout_orientation = "90";
line_length = "1825";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "2.787078";
max_framerate = "30";
min_exp_time = "22";
max_exp_time = "358733";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3327_ov491_out0: endpoint {
csi-port = <2>;
bus-width = <2>;
remote-endpoint = <&e3327_csi_in0>;
};
};
};
};
};
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* max_pixel_rate = <>;
* Max pixel rate in Kpixel/s for the ISP ISO case
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <2>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <160000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
/**
* The general guideline for naming badge_info contains 3 parts, and is as follows,
* The first part is the camera_board_id for the module; if the module is in a FFD
* platform, then use the platform name for this part.
* The second part contains the position of the module, ex. “rear” or “front”.
* The third part contains the last 6 characters of a part number which is found
* in the module's specsheet from the vender.
*/
modules {
module0 {
badge = "e3327_front_P5V27C";
position = "rear";
orientation = "1";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ov491 2-0024";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/ov491_a@24";
};
};
};
};
};
My source code
/*
* ov491.c - ov491 isp driver
*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <media/tegra_v4l2_camera.h>
#include <media/tegra-v4l2-camera.h>
#include <media/camera_common.h>
#include "ov491_mode_tbls.h"
#define OV491_DEFAULT_MODE OV491_MODE_1824X940_CROP_30FPS
#define OV491_DEFAULT_DATAFMT MEDIA_BUS_FMT_SBGGR10_1X10 // 나중에 check SRGGB가 아닐것
//#define OV491_DEFAULT_DATAFMT MEDIA_BUS_FMT_YUYV8_1_5X8 // ??? YUV인것 인가?
#define OV491_DEFAULT_WIDTH 1824
#define OV491_DEFAULT_HEIGHT 940
#define OV491_DEFAULT_CLK_FREQ 24000000
#define OV491_GAIN_ADDR 0xC103
#define OV491_FUSE_ID_ADDR 0x3D00 // ov5693에서 가져온것
#define OV491_FUSE_ID_OTP_BANK 0
#define OV491_FUSE_ID_SIZE 8
#define OV491_FUSE_ID_STR_SIZE (OV491_FUSE_ID_SIZE * 2)
/*ADDR */
#define OV491_SW_RESET_ADDR0 0x3011 // 0xF0
#define OV491_SW_RESET_ADDR1 0x3017 // 0xF0
struct ov491 {
struct camera_common_power_rail power;
int numctrls;
struct v4l2_ctrl_handler ctrl_handler;
struct i2c_client *i2c_client;
struct v4l2_subdev *subdev;
struct media_pad pad;
u32 frame_length;
s32 group_hold_prev;
bool group_hold_en;
s64 last_wdr_et_val;
struct regmap *regmap;
struct camera_common_data *s_data;
struct camera_common_pdata *pdata;
struct v4l2_ctrl *ctrls[];
};
static const struct regmap_config sensor_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.use_single_rw = true,
};
static int ov491_g_volatile_ctrl(struct v4l2_ctrl *ctrl);
static int ov491_s_ctrl(struct v4l2_ctrl *ctrl);
static const struct v4l2_ctrl_ops ov491_ctrl_ops = {
.g_volatile_ctrl = ov491_g_volatile_ctrl,
.s_ctrl = ov491_s_ctrl,
};
static const struct media_entity_operations ov491_media_ops = {
.link_validate = v4l2_subdev_link_validate,
};
static inline int ov491_read_reg(struct camera_common_data *s_data,
u16 addr, u8 *val)
{
struct ov491 *priv = (struct ov491 *)s_data->priv;
int err = 0;
u32 reg_val = 0;
pr_info("[OV491]: i2c read addr : 0x%x\n",addr);
err = regmap_read(priv->regmap, addr, ®_val);
*val = reg_val & 0xFF;
pr_info("[OV491]: i2c read val : 0x%x\n",reg_val);
return err;
}
static int ov491_write_reg(struct camera_common_data *s_data,
u16 addr, u8 val)
{
int err;
struct ov491 *priv = (struct ov491 *)s_data->priv;
pr_info("[OV491]: i2c write addr : 0x%x\n",addr);
err = regmap_write(priv->regmap, addr, val);
if (err)
pr_err("%s:i2c write failed, 0x%x = %x\n",
__func__, addr, val);
pr_info("[OV491]: i2c write val : 0x%x\n",reg_val);
return err;
}
static int ov491_power_on(struct camera_common_data *s_data)
{
int err = 0;
struct ov491 *priv = (struct ov491 *)s_data->priv;
struct camera_common_power_rail *pw = &priv->power;
dev_dbg(&priv->i2c_client->dev, "%s: power on\n", __func__);
if (priv->pdata && priv->pdata->power_on) {
err = priv->pdata->power_on(pw);
if (err)
pr_err("%s failed.\n", __func__);
else
pw->state = SWITCH_ON;
return err;
}
/*exit reset mode: XCLR */
if (pw->reset_gpio) {
gpio_set_value(pw->reset_gpio, 0);
usleep_range(30, 50);
gpio_set_value(pw->reset_gpio, 1);
usleep_range(30, 50);
}
pw->state = SWITCH_ON;
return 0;
}
static int ov491_power_off(struct camera_common_data *s_data)
{
int err = 0;
struct ov491 *priv = (struct ov491 *)s_data->priv;
struct camera_common_power_rail *pw = &priv->power;
dev_dbg(&priv->i2c_client->dev, "%s: power off\n", __func__);
if (priv->pdata && priv->pdata->power_off) {
err = priv->pdata->power_off(pw);
if (!err)
goto power_off_done;
else
pr_err("%s failed.\n", __func__);
return err;
}
/* enter reset mode: XCLR */
usleep_range(1, 2);
if (pw->reset_gpio)
gpio_set_value(pw->reset_gpio, 0);
power_off_done:
pw->state = SWITCH_OFF;
return 0;
}
static int ov491_power_get(struct ov491 *priv)
{
struct camera_common_power_rail *pw = &priv->power;
struct camera_common_pdata *pdata = priv->pdata;
const char *mclk_name;
struct clk *parent;
int err = 0;
mclk_name = priv->pdata->mclk_name ?
priv->pdata->mclk_name : "extperiph1";
pw->mclk = devm_clk_get(&priv->i2c_client->dev, mclk_name);
if (IS_ERR(pw->mclk)) {
dev_err(&priv->i2c_client->dev,
"unable to get clock %s\n", mclk_name);
return PTR_ERR(pw->mclk);
}
parent = devm_clk_get(&priv->i2c_client->dev, "pllp_grtba");
if (IS_ERR(parent))
dev_err(&priv->i2c_client->dev, "devm_clk_get failed for pllp_grtba");
else
clk_set_parent(pw->mclk, parent);
pw->reset_gpio = pdata->reset_gpio;
pw->state = SWITCH_OFF;
return err;
}
/*
static int ov491_write_table(struct ov491 *priv,
const ov491_reg table[])
{
return regmap_util_write_table_8(priv->regmap,
table,
NULL, 0,
OV491_TABLE_WAIT_MS,
OV491_TABLE_END);
}
*/
static int ov491_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct camera_common_data *s_data = to_camera_common_data(&client->dev);
struct ov491 *priv = (struct ov491 *)s_data->priv;
struct camera_common_power_rail *pw = &priv->power;
*status = pw->state == SWITCH_ON;
return 0;
}
static inline void ov491_get_gain_reg(ov491_reg *regs,
u8 gain)
{
regs->addr = OV491_GAIN_ADDR;
regs->val = (gain) & 0xff;
}
static int ov491_set_gain(struct ov491 *priv, s64 val)
{
ov491_reg reg_list[1];
int err;
u8 gain;
/* translate value */
gain = (u8) (val * 160 / (48 * FIXED_POINT_SCALING_FACTOR));
dev_dbg(&priv->i2c_client->dev,
"%s: gain reg: %d\n", __func__, gain);
ov491_get_gain_reg(reg_list, gain);
err = ov491_write_reg(priv->s_data, reg_list[0].addr,
reg_list[0].val);
if (err)
goto fail;
return 0;
fail:
dev_dbg(&priv->i2c_client->dev,
"%s: GAIN control error\n", __func__);
return err;
}
static int ov491_set_frame_rate(struct ov491 *priv, s64 val)
{
//ov491_reg reg_list[3];
//int err;
u32 frame_length;
struct camera_common_data *s_data = priv->s_data;
const struct sensor_mode_properties *mode =
&s_data->sensor_props.sensor_modes[s_data->mode];
//struct v4l2_control control;
//int hdr_en;
//int i = 0;
frame_length = mode->signal_properties.pixel_clock.val *
FIXED_POINT_SCALING_FACTOR /
mode->image_properties.line_length / val;
priv->frame_length = frame_length;
//if (priv->frame_length > OV491_MAX_FRAME_LENGTH)
// priv->frame_length = OV491_MAX_FRAME_LENGTH;
dev_dbg(&priv->i2c_client->dev,
"%s: val: %lld, , frame_length: %d\n", __func__,
val, priv->frame_length);
//ov491_get_frame_length_regs(reg_list, priv->frame_length); // ov491은 frame length 가 없다??
/*
for (i = 0; i < 3; i++) {
err = ov491_write_reg(priv->s_data, reg_list[i].addr,
reg_list[i].val);
if (err)
goto fail;
}
*/
/* check hdr enable ctrl */ // 아직 쓸때가 아니다.
/*
control.id = TEGRA_CAMERA_CID_HDR_EN;
err = camera_common_g_ctrl(priv->s_data, &control);
if (err < 0) {
dev_err(&priv->i2c_client->dev,
"could not find device ctrl.\n");
return err;
}
hdr_en = switch_ctrl_qmenu[control.value];
if ((hdr_en == SWITCH_ON) && (priv->last_wdr_et_val != 0)) {
err = imx185_set_coarse_time_hdr(priv, priv->last_wdr_et_val);
if (err)
dev_dbg(&priv->i2c_client->dev,
"%s: error coarse time SHS1 SHS2 override\n", __func__);
}
*/
return 0;
/*
fail:
dev_dbg(&priv->i2c_client->dev,
"%s: FRAME_LENGTH control error\n", __func__);
return err;
*/
}
static int ov491_set_exposure(struct ov491 *priv, s64 val)
{
int err;
struct v4l2_control control;
//int hdr_en;
dev_dbg(&priv->i2c_client->dev,
"%s: val: %lld\n", __func__, val);
/* check hdr enable ctrl */
control.id = TEGRA_CAMERA_CID_HDR_EN;
err = camera_common_g_ctrl(priv->s_data, &control);
if (err < 0) {
dev_err(&priv->i2c_client->dev,
"could not find device ctrl.\n");
return err;
}
/*
hdr_en = switch_ctrl_qmenu[control.value];
if (hdr_en == SWITCH_ON) {
err = imx185_set_coarse_time_hdr(priv, val);
if (err)
dev_dbg(&priv->i2c_client->dev,
"%s: error coarse time SHS1 SHS2 override\n", __func__);
} else {
err = imx185_set_coarse_time(priv, val);
if (err)
dev_dbg(&priv->i2c_client->dev,
"%s: error coarse time SHS1 override\n", __func__);
}
*/
return err;
}
static int ov491_s_stream(struct v4l2_subdev *sd, int enable)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct camera_common_data *s_data = to_camera_common_data(&client->dev);
struct ov491 *priv = (struct ov491 *)s_data->priv;
struct v4l2_ext_controls ctrls;
struct v4l2_ext_control control[3];
int err;
u8 test_val = 0;
dev_dbg(&client->dev, "%s++ enable %d\n", __func__, enable);
pr_info("[OV491]: streaming start.\n");
if (!enable) {
/* SW_RESET will have no ACK */
err = ov491_read_reg(s_data, OV491_SW_RESET_ADDR0, &test_val);
err = ov491_read_reg(s_data, OV491_SW_RESET_ADDR1, &test_val);
regmap_write(priv->regmap, OV491_SW_RESET_ADDR0, 0xFF);
regmap_write(priv->regmap, OV491_SW_RESET_ADDR1, 0x04);
/* Wait for one frame to make sure sensor is set to
* software standby in V-blank
*
* delay = frame length rows * Tline (10 us)
*/
usleep_range(priv->frame_length * 10,
priv->frame_length * 10 + 1000);
return 0;
}
if (s_data->override_enable) {
/* write list of override regs for the asking gain, */
/* frame rate and exposure time */
pr_info("[OV491]: streaming check.\n");
memset(&ctrls, 0, sizeof(ctrls));
ctrls.ctrl_class = V4L2_CTRL_ID2CLASS(TEGRA_CAMERA_CID_GAIN);
ctrls.count = 3;
ctrls.controls = control;
control[0].id = TEGRA_CAMERA_CID_GAIN;
control[1].id = TEGRA_CAMERA_CID_FRAME_RATE;
control[2].id = TEGRA_CAMERA_CID_EXPOSURE;
err = v4l2_g_ext_ctrls(&priv->ctrl_handler, &ctrls);
if (err == 0) {
err |= ov491_set_gain(priv, control[0].value64); //0xC103
if (err)
dev_err(&client->dev,
"%s: error gain override\n", __func__);
err |= ov491_set_frame_rate(priv, control[1].value64);
if (err)
dev_err(&client->dev,
"%s: error frame length override\n",
__func__);
err |= ov491_set_exposure(priv, control[2].value64);
if (err)
dev_err(&client->dev,
"%s: error exposure override\n",
__func__);
} else {
dev_err(&client->dev, "%s: faile to get overrides\n",
__func__);
}
}
/*
if (test_mode) {
err = ov491_write_table(priv,
mode_table[OV491_MODE_TEST_PATTERN]);
if (err)
goto exit;
}
*/
err |= regmap_write(priv->regmap, OV491_SW_RESET_ADDR0, 0x00);
err |= regmap_write(priv->regmap, OV491_SW_RESET_ADDR1, 0x00);
if (err)
goto exit;
return 0;
exit:
dev_err(&client->dev, "%s: error setting stream\n", __func__);
return err;
}
// open
static int ov491_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
dev_dbg(&client->dev, "%s:\n", __func__);
return 0;
}
static const struct v4l2_subdev_internal_ops ov491_subdev_internal_ops = {
.open = ov491_open,
};
static struct v4l2_subdev_core_ops ov491_subdev_core_ops = {
.s_power = camera_common_s_power,
};
static struct v4l2_subdev_video_ops ov491_subdev_video_ops = {
.s_stream = ov491_s_stream,
.g_mbus_config = camera_common_g_mbus_config,
.g_input_status = ov491_g_input_status,
};
static int ov491_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
return camera_common_g_fmt(sd, &format->format);
}
static int ov491_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
int ret;
if (format->which == V4L2_SUBDEV_FORMAT_TRY)
ret = camera_common_try_fmt(sd, &format->format);
else
ret = camera_common_s_fmt(sd, &format->format);
return ret;
}
static struct v4l2_subdev_pad_ops ov491_subdev_pad_ops = {
.set_fmt = ov491_set_fmt,
.get_fmt = ov491_get_fmt,
.enum_mbus_code = camera_common_enum_mbus_code,
.enum_frame_size = camera_common_enum_framesizes,
.enum_frame_interval = camera_common_enum_frameintervals,
};
static struct v4l2_subdev_ops ov491_subdev_ops = {
.core = &ov491_subdev_core_ops,
.video = &ov491_subdev_video_ops,
.pad = &ov491_subdev_pad_ops,
};
static struct v4l2_ctrl_config ctrl_config_list[] = {
/* Do not change the name field for the controls! */
{
.ops = &ov491_ctrl_ops,
.id = TEGRA_CAMERA_CID_GAIN,
.name = "Gain",
.type = V4L2_CTRL_TYPE_INTEGER64,
.flags = V4L2_CTRL_FLAG_SLIDER,
.min = 0 * FIXED_POINT_SCALING_FACTOR,
.max = 48 * FIXED_POINT_SCALING_FACTOR,
.def = 0 * FIXED_POINT_SCALING_FACTOR,
.step = 3 * FIXED_POINT_SCALING_FACTOR / 10, /* 0.3 db */
},
{
.ops = &ov491_ctrl_ops,
.id = TEGRA_CAMERA_CID_EXPOSURE,
.name = "Exposure",
.type = V4L2_CTRL_TYPE_INTEGER64,
.flags = V4L2_CTRL_FLAG_SLIDER,
.min = 30 * FIXED_POINT_SCALING_FACTOR / 1000000,
.max = 1000000LL * FIXED_POINT_SCALING_FACTOR / 1000000,
.def = 30 * FIXED_POINT_SCALING_FACTOR / 1000000,
.step = 1 * FIXED_POINT_SCALING_FACTOR / 1000000,
},
{
.ops = &ov491_ctrl_ops,
.id = TEGRA_CAMERA_CID_FRAME_RATE,
.name = "Frame Rate",
.type = V4L2_CTRL_TYPE_INTEGER64,
.flags = V4L2_CTRL_FLAG_SLIDER,
.min = 1 * FIXED_POINT_SCALING_FACTOR,
.max = 60 * FIXED_POINT_SCALING_FACTOR,
.def = 30 * FIXED_POINT_SCALING_FACTOR,
.step = 1 * FIXED_POINT_SCALING_FACTOR,
},
{
.ops = &ov491_ctrl_ops,
.id = TEGRA_CAMERA_CID_GROUP_HOLD,
.name = "Group Hold",
.type = V4L2_CTRL_TYPE_INTEGER_MENU,
.min = 0,
.max = ARRAY_SIZE(switch_ctrl_qmenu) - 1,
.menu_skip_mask = 0,
.def = 0,
.qmenu_int = switch_ctrl_qmenu,
},
{
.ops = &ov491_ctrl_ops,
.id = TEGRA_CAMERA_CID_HDR_EN,
.name = "HDR enable",
.type = V4L2_CTRL_TYPE_INTEGER_MENU,
.min = 0,
.max = ARRAY_SIZE(switch_ctrl_qmenu) - 1,
.menu_skip_mask = 0,
.def = 0,
.qmenu_int = switch_ctrl_qmenu,
},
{
.ops = &ov491_ctrl_ops,
.id = TEGRA_CAMERA_CID_FUSE_ID,
.name = "Fuse ID",
.type = V4L2_CTRL_TYPE_STRING,
.flags = V4L2_CTRL_FLAG_READ_ONLY,
.min = 0,
.max = OV491_FUSE_ID_STR_SIZE,
.step = 2,
},
{
.ops = &ov491_ctrl_ops,
.id = TEGRA_CAMERA_CID_SENSOR_MODE_ID,
.name = "Sensor Mode",
.type = V4L2_CTRL_TYPE_INTEGER64,
.flags = V4L2_CTRL_FLAG_SLIDER,
.min = 0,
.max = 0xFF,
.def = 0xFE,
.step = 1,
},
};
static struct camera_common_sensor_ops ov491_common_ops = {
.power_on = ov491_power_on,
.power_off = ov491_power_off,
.write_reg = ov491_write_reg,
.read_reg = ov491_read_reg,
};
static int ov491_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
{
struct ov491 *priv =
container_of(ctrl->handler, struct ov491, ctrl_handler);
int err = 0;
if (priv->power.state == SWITCH_OFF)
return 0;
switch (ctrl->id) {
default:
pr_err("%s: unknown ctrl id.\n", __func__);
return -EINVAL;
}
return err;
}
static int ov491_fuse_id_setup(struct ov491 *priv)
{
int err;
int i;
struct i2c_client *client = v4l2_get_subdevdata(priv->subdev);
struct camera_common_data *s_data = to_camera_common_data(&client->dev);
struct v4l2_ctrl *ctrl;
u8 fuse_id[OV491_FUSE_ID_SIZE];
u8 bak = 0;
err = camera_common_s_power(priv->subdev, true);
if (err)
return -ENODEV;
for (i = 0; i < OV491_FUSE_ID_SIZE; i++) {
err |= ov491_read_reg(s_data,
OV491_FUSE_ID_ADDR + i, &bak);
if (!err)
fuse_id[i] = bak;
else {
pr_err("%s: can not read fuse id\n", __func__);
return -EINVAL;
}
}
ctrl = v4l2_ctrl_find(&priv->ctrl_handler, TEGRA_CAMERA_CID_FUSE_ID);
if (!ctrl) {
dev_err(&priv->i2c_client->dev,
"could not find device ctrl.\n");
return -EINVAL;
}
for (i = 0; i < OV491_FUSE_ID_SIZE; i++)
sprintf(&ctrl->p_new.p_char[i*2], "%02x",
fuse_id[i]);
ctrl->p_cur.p_char = ctrl->p_new.p_char;
dev_info(&client->dev, "%s, fuse id: %s\n", __func__,
ctrl->p_cur.p_char);
err = camera_common_s_power(priv->subdev, false);
if (err)
return -ENODEV;
return 0;
}
static int ov491_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct ov491 *priv =
container_of(ctrl->handler, struct ov491, ctrl_handler);
struct camera_common_data *s_data = priv->s_data;
int err = 0;
if (priv->power.state == SWITCH_OFF)
return 0;
switch (ctrl->id) {
case TEGRA_CAMERA_CID_GAIN:
//err = ov491_set_gain(priv, *ctrl->p_new.p_s64);
break;
case TEGRA_CAMERA_CID_EXPOSURE:
//err = ov491_set_exposure(priv, *ctrl->p_new.p_s64);
break;
case TEGRA_CAMERA_CID_FRAME_RATE:
//err = ov491_set_frame_rate(priv, *ctrl->p_new.p_s64);
break;
case TEGRA_CAMERA_CID_GROUP_HOLD:
//err = ov491_set_group_hold(priv, ctrl->val);
break;
case TEGRA_CAMERA_CID_HDR_EN:
break;
case TEGRA_CAMERA_CID_SENSOR_MODE_ID:
s_data->sensor_mode_id = (int) (*ctrl->p_new.p_s64);
break;
default:
pr_err("%s: unknown ctrl id.\n", __func__);
return -EINVAL;
}
return err;
}
const struct of_device_id ov491_of_match[] = {
{ .compatible = "nvidia,ov491",},
{ },
};
static int ov491_ctrls_init(struct ov491 *priv)
{
struct i2c_client *client = priv->i2c_client;
struct v4l2_ctrl *ctrl;
int num_ctrls;
int err;
int i;
pr_info("[OV491]: ov0491_ctrl init.\n");
dev_dbg(&client->dev, "%s++\n", __func__);
num_ctrls = ARRAY_SIZE(ctrl_config_list);
v4l2_ctrl_handler_init(&priv->ctrl_handler, num_ctrls);
for (i = 0; i < num_ctrls; i++) {
ctrl = v4l2_ctrl_new_custom(&priv->ctrl_handler,
&ctrl_config_list[i], NULL);
if (ctrl == NULL) {
dev_err(&client->dev, "Failed to init %s ctrl\n",
ctrl_config_list[i].name);
continue;
}
if (ctrl_config_list[i].type == V4L2_CTRL_TYPE_STRING &&
ctrl_config_list[i].flags & V4L2_CTRL_FLAG_READ_ONLY) {
ctrl->p_new.p_char = devm_kzalloc(&client->dev,
ctrl_config_list[i].max + 1, GFP_KERNEL);
}
priv->ctrls[i] = ctrl;
}
priv->numctrls = num_ctrls;
priv->subdev->ctrl_handler = &priv->ctrl_handler;
if (priv->ctrl_handler.error) {
dev_err(&client->dev, "Error %d adding controls\n",
priv->ctrl_handler.error);
err = priv->ctrl_handler.error;
goto error;
}
err = v4l2_ctrl_handler_setup(&priv->ctrl_handler);
if (err) {
dev_err(&client->dev,
"Error %d setting default controls\n", err);
goto error;
}
err = ov491_fuse_id_setup(priv);
if (err) {
dev_err(&client->dev,
"Error %d reading fuse id data\n", err);
goto error;
}
return 0;
error:
v4l2_ctrl_handler_free(&priv->ctrl_handler);
return err;
}
MODULE_DEVICE_TABLE(of, ov491_of_match);
static struct camera_common_pdata *ov491_parse_dt(struct i2c_client *client,
struct camera_common_data *s_data)
{
struct device_node *np = client->dev.of_node;
struct camera_common_pdata *board_priv_pdata;
const struct of_device_id *match;
int err;
const char *str;
if (!np)
return NULL;
match = of_match_device(ov491_of_match, &client->dev);
if (!match) {
pr_info("[OV491]: Failed to find matching dt id.\n");
dev_err(&client->dev, "Failed to find matching dt id\n");
return NULL;
}
err = of_property_read_string(np, "use_sensor_mode_id", &str);
if (!err) {
if (!strcmp(str, "true"))
s_data->use_sensor_mode_id = true;
else
s_data->use_sensor_mode_id = false;
}
board_priv_pdata = devm_kzalloc(&client->dev,
sizeof(*board_priv_pdata), GFP_KERNEL);
err = of_property_read_string(np, "mclk",
&board_priv_pdata->mclk_name);
if (err){
pr_info("[OV491]: mclk not in DT\n.\n");
dev_err(&client->dev, "mclk not in DT\n");
}
board_priv_pdata->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0);
if (err) {
dev_err(&client->dev, "reset-gpios not found %d\n", err);
board_priv_pdata->reset_gpio = 0;
}
return board_priv_pdata;
}
static int ov491_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct camera_common_data *common_data;
struct ov491 *priv;
int err;
u8 test_val = 0;
dev_info(&client->dev, "[OV491]: probing v4l2 sensor at addr 0x%0x.\n",
client->addr);
common_data = devm_kzalloc(&client->dev,
sizeof(struct camera_common_data), GFP_KERNEL);
priv = devm_kzalloc(&client->dev,
sizeof(struct ov491) + sizeof(struct v4l2_ctrl *) *
ARRAY_SIZE(ctrl_config_list),
GFP_KERNEL);
if (!priv) {
dev_err(&client->dev, "unable to allocate memory!\n");
return -ENOMEM;
}
pr_info("[OV491]: probing v4l2 sensor.\n");
priv->regmap = devm_regmap_init_i2c(client, &sensor_regmap_config);
if (IS_ERR(priv->regmap)) {
pr_info("[OV491]: check regmap.\n");
dev_err(&client->dev,
"regmap init failed: %ld\n", PTR_ERR(priv->regmap));
return -ENODEV;
}
if (client->dev.of_node)
priv->pdata = ov491_parse_dt(client, common_data);
if (!priv->pdata) {
dev_err(&client->dev, "unable to get platform data\n");
return -EFAULT;
}
common_data->ops = &ov491_common_ops;
common_data->ctrl_handler = &priv->ctrl_handler;
common_data->dev = &client->dev;
//priv->code = MEDIA_BUS_FMT_YUYV8_2X8;
//priv->colorspace = V4L2_COLORSPACE_JPEG;
common_data->frmfmt = &ov491_frmfmt[0];
common_data->colorfmt = camera_common_find_datafmt(
OV491_DEFAULT_DATAFMT); // 여기 체크 색....
//common_data->colorfmt = V4L2_COLORSPACE_JPEG;
common_data->power = &priv->power;
common_data->ctrls = priv->ctrls;
common_data->priv = (void *)priv;
common_data->numctrls = ARRAY_SIZE(ctrl_config_list);
common_data->numfmts = ARRAY_SIZE(ov491_frmfmt);
common_data->def_mode = OV491_DEFAULT_MODE;
common_data->def_width = OV491_DEFAULT_WIDTH;
common_data->def_height = OV491_DEFAULT_HEIGHT;
common_data->fmt_width = common_data->def_width;
common_data->fmt_height = common_data->def_height;
common_data->def_clk_freq = OV491_DEFAULT_CLK_FREQ;
priv->i2c_client = client;
priv->s_data = common_data;
priv->subdev = &common_data->subdev;
priv->subdev->dev = &client->dev;
priv->s_data->dev = &client->dev;
priv->last_wdr_et_val = 0;
err = ov491_power_get(priv);
if (err)
return err;
err = camera_common_initialize(common_data, "ov491");
if (err) {
dev_err(&client->dev, "Failed to initialize ov491.\n");
return err;
}
pr_info("[OV491]: Start read reg.\n");
err = ov491_read_reg(common_data, 0x3000, &test_val);
err = ov491_read_reg(common_data, OV491_SW_RESET_ADDR0, &test_val);
err = ov491_read_reg(common_data, OV491_SW_RESET_ADDR1, &test_val);
pr_info("[OV491]: end read reg.\n");
v4l2_i2c_subdev_init(priv->subdev, client, &ov491_subdev_ops);
err = ov491_ctrls_init(priv);
if (err)
return err;
priv->subdev->internal_ops = &ov491_subdev_internal_ops;
priv->subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
V4L2_SUBDEV_FL_HAS_EVENTS;
#if defined(CONFIG_MEDIA_CONTROLLER)
priv->pad.flags = MEDIA_PAD_FL_SOURCE;
priv->subdev->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
priv->subdev->entity.ops = &ov491_media_ops;
err = media_entity_init(&priv->subdev->entity, 1, &priv->pad, 0);
if (err < 0) {
dev_err(&client->dev, "unable to init media entity\n");
return err;
}
#endif
err = v4l2_async_register_subdev(priv->subdev);
if (err)
return err;
dev_info(&client->dev, "Detected OV491 sensor\n");
return 0;
}
static int ov491_remove(struct i2c_client *client)
{
struct camera_common_data *s_data = to_camera_common_data(&client->dev);
struct ov491 *priv = (struct ov491 *)s_data->priv;
v4l2_async_unregister_subdev(priv->subdev);
#if defined(CONFIG_MEDIA_CONTROLLER)
media_entity_cleanup(&priv->subdev->entity);
#endif
v4l2_ctrl_handler_free(&priv->ctrl_handler);
camera_common_cleanup(s_data);
return 0;
}
static const struct i2c_device_id ov491_id[] = {
{ "ov491", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ov491_id);
static struct i2c_driver ov491_i2c_driver = {
.driver = {
.name = "ov491",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(ov491_of_match),
},
.probe = ov491_probe,
.remove = ov491_remove,
.id_table = ov491_id,
};
module_i2c_driver(ov491_i2c_driver);
MODULE_DESCRIPTION("Media Controller driver for OV491");
MODULE_AUTHOR("NVIDIA Corporation");
MODULE_LICENSE("GPL v2");
hello withmarine,
seems you’re working with YUV sensor, please note that “nvcamerasrc” did not support yuv sensors.
please use below commands to access yuv sensors instead, thanks
nvgstcapture-1.0
it work thank you jerrychang