IMX290 sensor fails on TX2 r32.1

Hi,

I have some trouble getting an IMX290 sensor to work on the TX2 with l4t r32.1. The same sensor works fine with the same driver and kernel on a Jetson Nano. I ported the driver from the 28.2.1 release. With the 28.2.1 release, this sensor also works fine on the TX2.

From the trace output it looks like the CSI module is complaining about a SHORT frame but the active_w and active_h values are the same as on the working version and are also just as expected.

See below for the device tree dtsi files, the output of dmesg and the output of the trace.

Any ideas what went wrong? Are there any other relevant changes since r28.2.1 which I overlooked?

Thanks,

/Arne

Device Tree:

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#include <t18x-common-modules/tegra186-camera-imx290-a00.dtsi>
#include "dt-bindings/clock/tegra186-clock.h"

#define CAM0_RST_L	TEGRA_MAIN_GPIO(R, 5)
#define CAM0_PWDN	TEGRA_MAIN_GPIO(R, 0)
#define CAM1_RST_L	TEGRA_MAIN_GPIO(R, 1)
#define CAM1_PWDN	TEGRA_MAIN_GPIO(L, 6)
#define CAMERA_I2C_MUX_BUS(x) (0x1E + x)

/* camera control gpio definitions */

/ {
	i2c@3180000 {
		imx290_a@1a {
			/* Define any required hw resources needed by driver */
			/* ie. clocks, io pins, power sources */
			clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>,
						<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
			clock-names = "extperiph1", "pllp_grtba";
			mclk = "extperiph1";
			reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
			pwdn-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
		};
	};
};
/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/ {
	host1x {
		vi@15700000 {
			num-channels = <1>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
				port@0 {
					status = "okay";
					reg = <0>;
					tisimx290_vi_in0: endpoint {
						status = "okay";
						port-index = <0>;
						bus-width = <2>;
						remote-endpoint = <&tisimx290_csi_out0>;
					};
				};
			};
		};

		nvcsi@150c0000 {
			num-channels = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			channel@0 {
				status = "okay";
				reg = <0>;
				ports {
					#address-cells = <1>;
					#size-cells = <0>;
					port@0 {
						status = "okay";
						reg = <0>;
						tisimx290_csi_in0: endpoint@0 {
							status = "okay";
							port-index = <0>;
							bus-width = <2>;
							remote-endpoint = <&tisimx290_imx290_out0>;
						};
					};
					port@1 {
						status = "okay";
						reg = <1>;
						tisimx290_csi_out0: endpoint@1 {
							status = "okay";
							remote-endpoint = <&tisimx290_vi_in0>;
						};
					};
				};
			};
		};
	};

	i2c@3180000 {
	tis_fpdlink-deser@30 {
			compatible = "tis,tis-fpdlink", "tis,tis-fpdlink-deser";
			status = "okay";
			reg = <0x30>;
			clkout_ctrl1 = /bits/ 8 <0x41>;
			clkout_ctrl2 = /bits/ 8 <0x1b>;
			slave_addr = /bits/ 8 <0x1a>;
			slave_map_addr = /bits/ 8 <0x1a>;
			ser_map_addr = /bits/ 8 <0x20>;
			ser_i2c_setup = /bits/ 8 <0x0d 0x0 0x0e 0x30 0x0d 0x02>;
	};

	imx290_a@1a {
		compatible = "nvidia,imx290";
		status = "okay";

		reg = <0x1a>;
		devnode = "video0";

		/* Physical dimensions of sensor */
		physical_w = "5.640";
		physical_h = "3.216";

		sensor_model ="imx290";
		/* Define any required hw resources needed by driver */
		/* ie. clocks, io pins, power sources */

		/* Defines number of frames to be dropped by driver internally after applying */
		/* sensor crop settings. Some sensors send corrupt frames after applying */
		/* crop co-ordinates */
		post_crop_frame_drop = "0";

		/* Convert Gain to unit of dB (decibel) befor passing to kernel driver */
		use_decibel_gain = "true";

		/* if true, delay gain setting by one frame to be in sync with exposure */
		delayed_gain = "true";

		/* enable CID_SENSOR_MODE_ID for sensor modes selection */
		use_sensor_mode_id = "true";

		/**
		* ==== Modes ====
		* A modeX node is required to support v4l2 driver
		* implementation with NVIDIA camera software stack
		*
		* == Signal properties ==
		*
		* phy_mode = "";
		* PHY mode used by the MIPI lanes for this device
		*
		* tegra_sinterface = "";
		* CSI Serial interface connected to tegra
		* Incase of virtual HW devices, use virtual
		* For SW emulated devices, use host
		*
		* pix_clk_hz = "";
		* Sensor pixel clock used for calculations like exposure and framerate
		*
		* readout_orientation = "0";
		* Based on camera module orientation.
		* Only change readout_orientation if you specifically
		* Program a different readout order for this mode
		*
		* == Image format Properties ==
		*
		* active_w = "";
		* Pixel active region width
		*
		* active_h = "";
		* Pixel active region height
		*
		* pixel_t = "";
		* The sensor readout pixel pattern
		*
		* line_length = "";
		* Pixel line length (width) for sensor mode.
		*
		* == Source Control Settings ==
		*
		* Gain factor used to convert fixed point integer to float
		* Gain range [min_gain/gain_factor, max_gain/gain_factor]
		* Gain step [step_gain/gain_factor is the smallest step that can be configured]
		* Default gain [Default gain to be initialized for the control.
						*     use min_gain_val as default for optimal results]
		* Framerate factor used to convert fixed point integer to float
		* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
		* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
		* Default Framerate [Default framerate to be initialized for the control.
						*     use max_framerate to get required performance]
		* Exposure factor used to convert fixed point integer to float
		* For convenience use 1 sec = 1000000us as conversion factor
		* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
		* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
		* Default Exposure Time [Default exposure to be initialized for the control.
						*     Set default exposure based on the default_framerate for optimal exposure settings]
		*
		* gain_factor = ""; (integer factor used for floating to fixed point conversion)
		* min_gain_val = ""; (ceil to integer)
		* max_gain_val = ""; (ceil to integer)
		* step_gain_val = ""; (ceil to integer)
		* default_gain = ""; (ceil to integer)
		* Gain limits for mode
		*
		* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
		* min_exp_time = ""; (ceil to integer)
		* max_exp_time = ""; (ceil to integer)
		* step_exp_time = ""; (ceil to integer)
		* default_exp_time = ""; (ceil to integer)
		* Exposure Time limits for mode (sec)
		*
		* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
		* min_framerate = ""; (ceil to integer)
		* max_framerate = ""; (ceil to integer)
		* step_framerate = ""; (ceil to integer)
		* default_framerate = ""; (ceil to integer)
		* Framerate limits for mode (fps)
		*
		* embedded_metadata_height = "";
		* Sensor embedded metadata height in units of rows.
		* If sensor does not support embedded metadata value should be 0.
		*/
		mode0 { /* IMX219_MODE_3280x2464_21FPS */
			mclk_khz = "24000";
			num_lanes = "2";
			tegra_sinterface = "serial_a";
			phy_mode = "DPHY";
			discontinuous_clk = "yes";
			dpcm_enable = "false";
			cil_settletime = "0";

			active_w = "1948";
			active_h = "1096";
			dynamic_pixel_bit_depth = "12";
			csi_pixel_bit_depth = "12";
			mode_type = "bayer";
			pixel_phase = "rggb";
			pixel_t = "bayer_rggb12";
			readout_orientation = "0";
			line_length = "2922";
			inherent_gain = "1";
			mclk_multiplier = "25";
			pix_clk_hz = "148500000";

			gain_factor = "16";
			framerate_factor = "1000000";
			exposure_factor = "1000000";
			min_gain_val = "1";
			max_gain_val = "30";
			step_gain_val = "1";
			default_gain = "1"; /* 1.00x */
			min_hdr_ratio = "1";
			max_hdr_ratio = "64";
			min_framerate = "2000000"; /* 2.0 fps */
			max_framerate = "60000000"; /* 21.0 fps */
			step_framerate = "1";
			default_framerate = "60000000"; /* 21.0 fps */
			min_exp_time = "15"; /* us */
			max_exp_time = "16650"; /* us */
			step_exp_time = "1";
			default_exp_time = "2495"; /* us */

			embedded_metadata_height = "2";
		};

		// mode1 { /* IMX219_MODE_640x480_10bit_maxFPS */
		// 	mclk_khz = "24000";
		// 	num_lanes = "2";
		// 	tegra_sinterface = "serial_c";
		// 	phy_mode = "DPHY";
		// 	discontinuous_clk = "yes";
		// 	dpcm_enable = "false";
		// 	cil_settletime = "0";

		// 	active_w = "640";
		// 	active_h = "480";
		// 	pixel_t = "bayer_rggb10";
		// 	readout_orientation = "0";
		// 	line_length = "2200";
		// 	inherent_gain = "1";
		// 	mclk_multiplier = "25";
		// 	pix_clk_hz = "148500000";

		// 	gain_factor = "16";
		// 	framerate_factor = "1000000";
		// 	exposure_factor = "1000000";
		// 	min_gain_val = "1";
		// 	max_gain_val = "30";
		// 	step_gain_val = "1";
		// 	default_gain = "1"; /* 1.00x */
		// 	min_hdr_ratio = "1";
		// 	max_hdr_ratio = "64";
		// 	min_framerate = "2000000"; /* 2.0 fps */
		// 	max_framerate = "60000000"; /* 21.0 fps */
		// 	step_framerate = "1";
		// 	default_framerate = "60000000"; /* 21.0 fps */
		// 	min_exp_time = "15"; /* us */
		// 	max_exp_time = "16650"; /* us */
		// 	step_exp_time = "1";
		// 	default_exp_time = "2495"; /* us */

		// 	embedded_metadata_height = "2";
		// };
		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			status="okay";
			port@0 {
				reg = <0>;
				status="okay";
				tisimx290_imx290_out0: endpoint {
					status="okay";
					port-index = <0>;
					bus-width = <2>;
					remote-endpoint = <&tisimx290_csi_in0>;
					};
				};
			};
		};
	};
};

/ {

	tegra-camera-platform {
		compatible = "nvidia, tegra-camera-platform";
		/**
		* Physical settings to calculate max ISO BW
		*
		* num_csi_lanes = <>;
		* Total number of CSI lanes when all cameras are active
		*
		* max_lane_speed = <>;
		* Max lane speed in Kbit/s
		*
		* min_bits_per_pixel = <>;
		* Min bits per pixel
		*
		* vi_peak_byte_per_pixel = <>;
		* Max byte per pixel for the VI ISO case
		*
		* vi_bw_margin_pct = <>;
		* Vi bandwidth margin in percentage
		*
		* max_pixel_rate = <>;
		* Max pixel rate in Kpixel/s for the ISP ISO case
		*
		* isp_peak_byte_per_pixel = <>;
		* Max byte per pixel for the ISP ISO case
		*
		* isp_bw_margin_pct = <>;
		* Isp bandwidth margin in percentage
		*/
		num_csi_lanes = <2>;
		max_lane_speed = <1500000>;
		min_bits_per_pixel = <12>;
		vi_peak_byte_per_pixel = <2>;
		vi_bw_margin_pct = <25>;
		isp_peak_byte_per_pixel = <5>;
		isp_bw_margin_pct = <25>;

		/**
		 * The general guideline for naming badge_info contains 3 parts, and is as follows,
		 * The first part is the camera_board_id for the module; if the module is in a FFD
		 * platform, then use the platform name for this part.
		 * The second part contains the position of the module, ex. "rear" or "front".
		 * The third part contains the last 6 characters of a part number which is found
		 * in the module's specsheet from the vender.
		 */
		modules {
			module0 {
				badge = "imx290_bottom_tisimx290";
				position = "bottom";
				orientation = "0";
				status="okay";
				drivernode0 {
					/* Declare PCL support driver (classically known as guid)  */
					status="okay";
					pcl_id = "v4l2_sensor";
					/* Driver v4l2 device name */
					devname = "imx290 2-001a";
					/* Declare the device-tree hierarchy to driver instance */
					proc-device-tree = "/proc/device-tree/i2c@3180000/imx290_a@1a";
				};
			};
		};
	};
};

dmesg:

[   58.677180] imx290 2-001a: camera_common_mclk_enable: enable MCLK with 24000000 Hz
[   58.677505] imx290 2-001a: camera_common_dpd_disable: csi 0
[   58.679161] nvcsi 150c0000.nvcsi: csi_port: 0
[   58.686707] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   58.686713] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   58.686718] nvcsi 150c0000.nvcsi: csi4_stream_init
[   58.686728] nvcsi 150c0000.nvcsi: csi4_stream_config
[   58.686738] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   58.686743] nvcsi 150c0000.nvcsi: csi4_phy_config
[   58.686749] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   58.686758] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   58.686761] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   58.686765] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   58.686779] imx290 2-001a: set mode 0
[   58.859397] imx290 2-001a: imx290_start_streaming
[   59.319415] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   59.325777] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   59.335491] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   59.335495] nvcsi 150c0000.nvcsi: csi4_phy_config
[   59.335499] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   59.335504] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   59.335508] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   59.344259] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0001000c
[   59.352089] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0001000c
[   59.360304] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   59.360310] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   59.360312] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   59.360314] nvcsi 150c0000.nvcsi: csi4_stream_init
[   59.360323] nvcsi 150c0000.nvcsi: csi4_stream_config
[   59.360330] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   59.360332] nvcsi 150c0000.nvcsi: csi4_phy_config
[   59.360336] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   59.360342] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   59.360344] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   59.360346] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   59.579408] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   59.585763] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   59.595447] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   59.595450] nvcsi 150c0000.nvcsi: csi4_phy_config
[   59.595454] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   59.595459] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   59.595462] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   59.604168] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0000000c
[   59.612042] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0000000c
[   59.620216] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   59.620221] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   59.620223] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   59.620225] nvcsi 150c0000.nvcsi: csi4_stream_init
[   59.620234] nvcsi 150c0000.nvcsi: csi4_stream_config
[   59.620242] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   59.620243] nvcsi 150c0000.nvcsi: csi4_phy_config
[   59.620248] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   59.620253] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   59.620255] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   59.620257] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   59.835413] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   59.841770] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   59.851469] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   59.851472] nvcsi 150c0000.nvcsi: csi4_phy_config
[   59.851476] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   59.851481] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   59.851484] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   59.860235] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0000000c
[   59.868064] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0000000c
[   59.876236] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   59.876241] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   59.876243] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   59.876245] nvcsi 150c0000.nvcsi: csi4_stream_init
[   59.876254] nvcsi 150c0000.nvcsi: csi4_stream_config
[   59.876261] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   59.876262] nvcsi 150c0000.nvcsi: csi4_phy_config
[   59.876267] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   59.876272] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   59.876274] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   59.876276] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   60.095419] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   60.101774] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   60.111483] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   60.111486] nvcsi 150c0000.nvcsi: csi4_phy_config
[   60.111490] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   60.111495] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   60.111498] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   60.120202] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0001000c
[   60.128074] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0001000c
[   60.136248] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   60.136253] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   60.136255] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   60.136257] nvcsi 150c0000.nvcsi: csi4_stream_init
[   60.136266] nvcsi 150c0000.nvcsi: csi4_stream_config
[   60.136274] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   60.136277] nvcsi 150c0000.nvcsi: csi4_phy_config
[   60.136282] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   60.136287] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   60.136289] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   60.136291] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   60.351419] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   60.357775] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   60.367480] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   60.367482] nvcsi 150c0000.nvcsi: csi4_phy_config
[   60.367486] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   60.367491] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   60.367494] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   60.376200] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0000000c
[   60.384072] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0000000c
[   60.392247] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   60.392252] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   60.392254] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   60.392255] nvcsi 150c0000.nvcsi: csi4_stream_init
[   60.392264] nvcsi 150c0000.nvcsi: csi4_stream_config
[   60.392271] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   60.392273] nvcsi 150c0000.nvcsi: csi4_phy_config
[   60.392277] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   60.392283] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   60.392284] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   60.392286] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   60.611406] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   60.617760] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   60.627451] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   60.627453] nvcsi 150c0000.nvcsi: csi4_phy_config
[   60.627458] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   60.627463] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   60.627467] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   60.636171] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0000000c
[   60.644043] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0000000c
[   60.652217] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   60.652223] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   60.652225] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   60.652226] nvcsi 150c0000.nvcsi: csi4_stream_init
[   60.652235] nvcsi 150c0000.nvcsi: csi4_stream_config
[   60.652242] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   60.652244] nvcsi 150c0000.nvcsi: csi4_phy_config
[   60.652248] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   60.652254] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   60.652257] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   60.652260] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   60.871418] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   60.877819] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   60.887477] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   60.887479] nvcsi 150c0000.nvcsi: csi4_phy_config
[   60.887483] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   60.887488] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   60.887491] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   60.896240] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0000000c
[   60.904069] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0000000c
[   60.912288] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   60.912293] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   60.912295] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   60.912296] nvcsi 150c0000.nvcsi: csi4_stream_init
[   60.912305] nvcsi 150c0000.nvcsi: csi4_stream_config
[   60.912312] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   60.912314] nvcsi 150c0000.nvcsi: csi4_phy_config
[   60.912318] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   60.912324] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   60.912325] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   60.912327] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   61.127420] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   61.133779] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   61.143422] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   61.143425] nvcsi 150c0000.nvcsi: csi4_phy_config
[   61.143429] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   61.143435] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   61.143438] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   61.152190] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0000000c
[   61.160021] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0000000c
[   61.168237] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   61.168242] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   61.168244] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   61.168246] nvcsi 150c0000.nvcsi: csi4_stream_init
[   61.168255] nvcsi 150c0000.nvcsi: csi4_stream_config
[   61.168262] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   61.168264] nvcsi 150c0000.nvcsi: csi4_phy_config
[   61.168268] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   61.168274] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   61.168275] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   61.168277] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   61.387418] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   61.393774] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   61.403482] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   61.403484] nvcsi 150c0000.nvcsi: csi4_phy_config
[   61.403488] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   61.403493] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   61.403496] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   61.412248] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0000000c
[   61.420077] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0000000c
[   61.428295] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   61.428301] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   61.428302] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   61.428304] nvcsi 150c0000.nvcsi: csi4_stream_init
[   61.428313] nvcsi 150c0000.nvcsi: csi4_stream_config
[   61.428320] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   61.428322] nvcsi 150c0000.nvcsi: csi4_phy_config
[   61.428326] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   61.428331] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   61.428333] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   61.428335] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   61.643418] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   61.649818] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   61.659477] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   61.659479] nvcsi 150c0000.nvcsi: csi4_phy_config
[   61.659483] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   61.659488] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   61.659491] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   61.668242] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0000000c
[   61.676071] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0000000c
[   61.684289] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   61.684294] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   61.684296] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   61.684298] nvcsi 150c0000.nvcsi: csi4_stream_init
[   61.684306] nvcsi 150c0000.nvcsi: csi4_stream_config
[   61.684314] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   61.684315] nvcsi 150c0000.nvcsi: csi4_phy_config
[   61.684319] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   61.684325] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   61.684327] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   61.684329] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   61.903419] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   61.909775] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   61.919480] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   61.919482] nvcsi 150c0000.nvcsi: csi4_phy_config
[   61.919486] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   61.919491] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   61.919494] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   61.928244] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0001000c
[   61.936075] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0001000c
[   61.944254] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   61.944259] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   61.944261] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   61.944263] nvcsi 150c0000.nvcsi: csi4_stream_init
[   61.944272] nvcsi 150c0000.nvcsi: csi4_stream_config
[   61.944279] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   61.944281] nvcsi 150c0000.nvcsi: csi4_phy_config
[   61.944285] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   61.944291] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   61.944293] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   61.944295] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   62.159418] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   62.165819] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   62.175477] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   62.175479] nvcsi 150c0000.nvcsi: csi4_phy_config
[   62.175484] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   62.175488] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   62.175492] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   62.184238] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0001000c
[   62.192068] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0001000c
[   62.200283] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   62.200288] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   62.200290] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   62.200291] nvcsi 150c0000.nvcsi: csi4_stream_init
[   62.200300] nvcsi 150c0000.nvcsi: csi4_stream_config
[   62.200307] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   62.200309] nvcsi 150c0000.nvcsi: csi4_phy_config
[   62.200313] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   62.200319] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   62.200321] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   62.200322] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   62.419418] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   62.425775] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   62.435471] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   62.435473] nvcsi 150c0000.nvcsi: csi4_phy_config
[   62.435478] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   62.435482] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   62.435486] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   62.444190] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0001000c
[   62.452060] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0001000c
[   62.460234] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   62.460239] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   62.460241] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   62.460242] nvcsi 150c0000.nvcsi: csi4_stream_init
[   62.460251] nvcsi 150c0000.nvcsi: csi4_stream_config
[   62.460258] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   62.460260] nvcsi 150c0000.nvcsi: csi4_phy_config
[   62.460264] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   62.460270] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   62.460271] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   62.460275] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   62.679407] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[   62.685767] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[   62.695436] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   62.695439] nvcsi 150c0000.nvcsi: csi4_phy_config
[   62.695444] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   62.695449] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   62.695453] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   62.704161] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0000000c
[   62.712033] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0000000c
[   62.720208] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   62.720213] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[   62.720215] nvcsi 150c0000.nvcsi: csi4_start_streaming csi_port=0
[   62.720217] nvcsi 150c0000.nvcsi: csi4_stream_init
[   62.720226] nvcsi 150c0000.nvcsi: csi4_stream_config
[   62.720235] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[   62.720237] nvcsi 150c0000.nvcsi: csi4_phy_config
[   62.720241] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[   62.720247] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 148
[   62.720248] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[   62.720251] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 23
[   62.720674] imx290 2-001a: imx290_stop_streaming
[   62.725553] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[   62.725557] nvcsi 150c0000.nvcsi: csi4_phy_config
[   62.725564] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000002
[   62.725571] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[   62.725577] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x0000000c
[   62.734333] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x0000000c
[   62.742158] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x0000000c
[   62.750376] nvcsi 150c0000.nvcsi: csi4_cil_check_status 476
[   62.753311] imx290 2-001a: camera_common_dpd_enable: csi 0
[   62.753314] imx290 2-001a: camera_common_mclk_disable: disable MCLK

Trace:

root@jetson-tx2:~# cat /sys/kernel/debug/tracing/trace
# tracer: nop
#
# entries-in-buffer/entries-written: 745/745   #P:4
#
#                              _-----=> irqs-off
#                             / _----=> need-resched
#                            | / _---=> hardirq/softirq
#                            || / _--=> preempt-depth
#                            ||| /     delay
#           TASK-PID   CPU#  ||||    TIMESTAMP  FUNCTION
#              | |       |   ||||       |         |
     kworker/4:2-3003  [004] ....    49.707414: rtos_queue_peek_from_isr_failed: tstamp:1850679670 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    49.875400: rtos_queue_peek_from_isr_failed: tstamp:1855679673 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    50.043407: rtos_queue_peek_from_isr_failed: tstamp:1860679678 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    50.211402: rtos_queue_peek_from_isr_failed: tstamp:1865679686 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    50.379402: rtos_queue_peek_from_isr_failed: tstamp:1870679694 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    50.491401: rtos_queue_peek_from_isr_failed: tstamp:1875679700 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    50.659402: rtos_queue_peek_from_isr_failed: tstamp:1880679708 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    50.827402: rtos_queue_peek_from_isr_failed: tstamp:1885679714 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    50.995393: rtos_queue_peek_from_isr_failed: tstamp:1890679722 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    51.163402: rtos_queue_peek_from_isr_failed: tstamp:1895679728 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    51.331400: rtos_queue_peek_from_isr_failed: tstamp:1900679735 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    51.499402: rtos_queue_peek_from_isr_failed: tstamp:1905679741 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    51.611402: rtos_queue_peek_from_isr_failed: tstamp:1910679747 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    51.779402: rtos_queue_peek_from_isr_failed: tstamp:1915679755 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    51.947402: rtos_queue_peek_from_isr_failed: tstamp:1920679761 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    52.115402: rtos_queue_peek_from_isr_failed: tstamp:1925679769 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    52.283400: rtos_queue_peek_from_isr_failed: tstamp:1930679777 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    52.451402: rtos_queue_peek_from_isr_failed: tstamp:1935679782 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    52.619394: rtos_queue_peek_from_isr_failed: tstamp:1940679788 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    52.731392: rtos_queue_peek_from_isr_failed: tstamp:1945679794 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    52.899395: rtos_queue_peek_from_isr_failed: tstamp:1950679809 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    53.067403: rtos_queue_peek_from_isr_failed: tstamp:1955679811 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    53.235403: rtos_queue_peek_from_isr_failed: tstamp:1960679817 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    53.403410: rtos_queue_peek_from_isr_failed: tstamp:1965679836 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    53.571402: rtos_queue_peek_from_isr_failed: tstamp:1970679830 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    53.739391: rtos_queue_peek_from_isr_failed: tstamp:1975679835 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    53.851402: rtos_queue_peek_from_isr_failed: tstamp:1980679841 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    54.019396: rtos_queue_peek_from_isr_failed: tstamp:1985679851 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    54.187402: rtos_queue_peek_from_isr_failed: tstamp:1990679858 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    54.355525: rtos_queue_peek_from_isr_failed: tstamp:1995679865 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    54.523394: rtos_queue_peek_from_isr_failed: tstamp:2000679871 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    54.691395: rtos_queue_peek_from_isr_failed: tstamp:2005679877 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    54.859400: rtos_queue_peek_from_isr_failed: tstamp:2010679885 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    54.971402: rtos_queue_peek_from_isr_failed: tstamp:2015679893 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    55.139405: rtos_queue_peek_from_isr_failed: tstamp:2020442895 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    58.723412: rtos_queue_peek_from_isr_failed: tstamp:2131733356 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    58.723417: rtcpu_start: tstamp:2131734781
     kworker/4:2-3003  [004] ....    58.723419: rtos_queue_send_from_isr_failed: tstamp:2131743528 queue:0x0b4a7258
     kworker/4:2-3003  [004] ....    58.723420: rtos_queue_send_from_isr_failed: tstamp:2131743634 queue:0x0b4aad68
     kworker/4:2-3003  [004] ....    58.723422: rtos_queue_send_from_isr_failed: tstamp:2131743742 queue:0x0b4ac998
     kworker/4:2-3003  [004] ....    58.723423: rtos_queue_send_from_isr_failed: tstamp:2131743848 queue:0x0b4ae518
     kworker/4:2-3003  [004] ....    58.723424: rtos_queue_send_from_isr_failed: tstamp:2131743953 queue:0x0b4af2d8
     kworker/4:2-3003  [004] ....    58.723425: rtos_queue_send_from_isr_failed: tstamp:2131744064 queue:0x0b4b0098
     kworker/4:2-3003  [004] ....    58.723426: rtos_queue_send_from_isr_failed: tstamp:2131744167 queue:0x0b4b0e58
     kworker/4:2-3003  [004] ....    58.723427: rtos_queue_send_from_isr_failed: tstamp:2131744272 queue:0x0b4b1c18
     kworker/4:2-3003  [004] ....    58.723429: rtos_queue_send_failed: tstamp:2131744722 queue:0x0b4a7258
     kworker/4:2-3003  [004] ....    58.723430: rtos_queue_send_from_isr_failed: tstamp:2131746517 queue:0x0b4a7258
     kworker/4:2-3003  [004] ....    58.723431: rtos_queue_send_from_isr_failed: tstamp:2131746623 queue:0x0b4aad68
     kworker/4:2-3003  [004] ....    58.723432: rtos_queue_send_from_isr_failed: tstamp:2131746730 queue:0x0b4ac998
     kworker/4:2-3003  [004] ....    58.723433: rtos_queue_send_from_isr_failed: tstamp:2131746836 queue:0x0b4ae518
     kworker/4:2-3003  [004] ....    58.723435: rtos_queue_send_from_isr_failed: tstamp:2131746941 queue:0x0b4af2d8
     kworker/4:2-3003  [004] ....    58.723436: rtos_queue_send_from_isr_failed: tstamp:2131747046 queue:0x0b4b0098
     kworker/4:2-3003  [004] ....    58.723437: rtos_queue_send_from_isr_failed: tstamp:2131747152 queue:0x0b4b0e58
     kworker/4:2-3003  [004] ....    58.723438: rtos_queue_send_from_isr_failed: tstamp:2131747257 queue:0x0b4b1c18
     kworker/4:2-3003  [004] ....    58.723439: rtos_queue_send_failed: tstamp:2131748204 queue:0x0b4a7258
     kworker/4:2-3003  [004] ....    58.891405: rtos_queue_peek_from_isr_failed: tstamp:2136733687 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    58.891408: rtcpu_vinotify_event: tstamp:2137861603 tag:CSIMUX_FRAME channel:0x00 frame:1 vi_tstamp:2137861221 data:0x000000a0
     kworker/4:2-3003  [004] ....    58.947402: rtcpu_vinotify_event: tstamp:2138524788 tag:CSIMUX_FRAME channel:0x00 frame:2 vi_tstamp:2138524415 data:0x00c00060
     kworker/4:2-3003  [004] ....    58.947403: rtcpu_vinotify_event: tstamp:2139206700 tag:CSIMUX_FRAME channel:0x00 frame:3 vi_tstamp:2139206328 data:0x000000a0
     kworker/4:2-3003  [004] ....    58.947405: rtcpu_vinotify_event: tstamp:2139869895 tag:CSIMUX_FRAME channel:0x00 frame:4 vi_tstamp:2139869523 data:0x00c00060
     kworker/4:2-3003  [004] ....    59.003402: rtcpu_vinotify_event: tstamp:2140551808 tag:CSIMUX_FRAME channel:0x00 frame:5 vi_tstamp:2140551436 data:0x000000a0
     kworker/4:2-3003  [004] ....    59.003404: rtcpu_vinotify_event: tstamp:2141224361 tag:CSIMUX_FRAME channel:0x00 frame:6 vi_tstamp:2141223989 data:0x000000a0
     kworker/4:2-3003  [004] ....    59.059392: rtos_queue_peek_from_isr_failed: tstamp:2141733689 queue:0x0b4b4500
     kworker/4:2-3003  [004] ....    59.059393: rtcpu_vinotify_event: tstamp:2141887567 tag:CSIMUX_FRAME channel:0x00 frame:7 vi_tstamp:2141887183 data:0x00c00060
     kworker/4:2-3003  [004] ....    59.059394: rtcpu_vinotify_event: tstamp:2142569467 tag:CSIMUX_FRAME channel:0x00 frame:8 vi_tstamp:2142569096 data:0x000000a0
     kworker/4:2-3003  [004] ....    59.059395: rtcpu_vinotify_event: tstamp:2143232664 tag:CSIMUX_FRAME channel:0x00 frame:9 vi_tstamp:2143232290 data:0x00c00060
     kworker/4:2-3003  [004] ....    59.115403: rtcpu_vinotify_event: tstamp:2143914573 tag:CSIMUX_FRAME channel:0x00 frame:10 vi_tstamp:2143914203 data:0x000000a0
     kworker/4:2-3003  [004] ....    59.115405: rtcpu_vinotify_event: tstamp:2144587131 tag:CSIMUX_FRAME channel:0x00 frame:11 vi_tstamp:2144586756 data:0x000000a0
     kworker/4:2-3003  [004] ....    59.171403: rtcpu_vinotify_event: tstamp:2145250323 tag:CSIMUX_FRAME channel:0x00 frame:12 vi_tstamp:2145249951 data:0x00c00060
     kworker/4:2-3003  [004] ....    59.171404: rtcpu_vinotify_event: tstamp:2145260331 tag:ATOMP_FS channel:0x00 frame:13 vi_tstamp:2145259960 data:0x00000000
     kworker/4:2-3003  [004] ....    59.171405: rtcpu_vinotify_event: tstamp:2145277511 tag:CHANSEL_PXL_SOF channel:0x00 frame:13 vi_tstamp:2145277149 data:0x00000001
     kworker/4:2-3003  [004] ....    59.171406: rtcpu_vinotify_event: tstamp:2145278098 tag:CHANSEL_FAULT channel:0x00 frame:13 vi_tstamp:2145277735 data:0x00000200
     kworker/4:2-3003  [004] ....    59.171407: rtcpu_vinotify_event: tstamp:2145279011 tag:CHANSEL_LOAD_FRAMED channel:0x01 frame:13 vi_tstamp:2145278234 data:0x08000000
     kworker/4:2-3003  [004] ....    59.171408: rtcpu_vinotify_event: tstamp:2145279122 tag:CHANSEL_FAULT_FE channel:0x01 frame:13 vi_tstamp:2145278332 data:0x00000001
     kworker/4:2-3003  [004] ....    59.171409: rtcpu_vinotify_event: tstamp:2145279262 tag:ATOMP_FE channel:0x00 frame:13 vi_tstamp:2145278335 data:0x00000000
     kworker/4:2-3003  [004] ....    59.171410: rtos_queue_peek_from_isr_failed: tstamp:2146733696 queue:0x0b4b4500

Try to boost the vi/csi clock to try.

https://elinux.org/Jetson_TX2_Camera_BringUp

@ShaneCC

I tried boosting the clock as described in the camera bring up guide but the behaviour remains the same. Anything else I could try?

Below show PIXEL_SHORT_LINE means the output size not as expect.

kworker/4:2-3003  [004] ....    59.171406: rtcpu_vinotify_event: tstamp:2145278098 tag:CHANSEL_FAULT channel:0x00 frame:13 vi_tstamp:2145277735 data:0x00000200


CHANSEL_FAULT data bit field
    bit 16:31  LINE_NUMBER
    bit 15	DTYPE_MISMATCH
    bit 14	EMBED_INFRINGE
    bit 13	EMBED_LONG_LINE
    bit 12	EMBED_SPURIOUS
    bit 11	EMBED_RUNAWAY
    bit 10	EMBED_MISSING_LE
    bit 9	PIXEL_SHORT_LINE
    bit 8	PIXEL_LONG_LINE
    bit 7	PIXEL_SPURIOUS
    bit 6	PIXEL_RUNAWAY
    bit 5	PIXEL_MISSING_LE
    bit 4	PIXEL_LINE_TIMER
    bit 3	EMBED_EOF
    bit 2	EMBED_SOF
    bit 1	PIXEL_EOF
    bit 0	PIXEL_SOF

@ShaneCCC

Thanks. Actually the issue was that the sensor only sends 1 embedded data line instead of 2 I initially thought. Funny though that the R28.2 kernel on the Tx2 as well as the R32.1 kernel on the Nano do not fail, despite they are set to 2 embedded lines also.

TX2 from r32 release the embedded data lines must be correct precisely.