Increase the size of the TZDRAM on TX2

Hi,

So I have a custom trust-zone OS and applications that I would like to run on the TX2, but the amount of memory provided to the OS is very small (6MB).

So my understanding from the TRM, is that the TZDRAM’s aperture is programmable using the memory controllers registers. I see that this is done in the ARM-TF’s BL31 source code provided by nvidia, and I have tried increasing the size by modifying the ARM-TF’s BL31, but the accessible region of memory doesn’t seem to be affected by this change.

Does the BPMP do some additional work to setup the TZDRAM’s carevout that I don’t know about? I am thinking this might be the case since the aperture params (base and size) are passed from the BPMP, but it’s unclear why this is done. Is this memory region configurable in some way?

Thanks!

hello richard.habeeb,

according to Topic 163562, this TZDRAM_BASE variable in the makefile is actually is TZSRAM not the TZDRAM.
please see the mb1 header file for the carveout-id, and you should setup serial console and check the bootloader logs for the carveouts.
for example,

typedef enum carve_out_type {
..
  	CARVEOUT_TZDRAM = 32
[0001.444] I> Welcome to Cboot
[0001.447] I> Cboot Version: t186-02737b3e
[0001.451] I> CPU-BL Params @ 0x275800000
...
[0001.597] I> 32) Base:0x276000000 Size:0x00600000

Hi Jerry,

Thanks for your help. Reading between the lines of your post a bit, I realized that there is a configuration system for the MB1 that controls the carveout documented here. However when I compare the documentation of t186 and t194 MB1 configuration, I see that only the t194 seems to support parameters for tzdram size.

In short, the carveout.tzdram.size parameter seems to unavailable for the TX2. Is this true? Are there also parameters for adjusting the tzdram base? Is this possible to change in general or is it fixed in hardware?

My followup question would be this. What hardware system/controller is the MB1 interfacing with to setup this carveout?

Also, doesn’t the TX2 use TBoot or some proprietary Nvidia code for MB1 not CBoot? For anyone who is curious this head file is in the cboot sources (bootloader/partner/t18x/common/include/soc/t186/tegrabl_carveout_id.h)

Okay I have a solution to my original question, though admittedly this feels more like a hack. I’ll outline the steps.

So the only hardware needed to interface with to setup the TZDRAM aperture is the MC, which is programmed by ARM-TF BL31. If you update the function, “bl31_early_platform_setup” to modify the data structure passed from the BPMP: plat_params.tzdram_base, plat_params.tzdram_size, as well at the modify the entry_point_info_t data structure for the secure OS (this requires a messy const cast unfortunately). These assignments should happen before tegra_memctrl_tzdram_setup.

You will need to change the tzdram_base value because the carveout squeezes it between two other regions. You can find the original carveout printed out on the debug serial port. I used the following values:

  • tzdram_base = 0x260000000
  • tzdram_size = 0x10000000
  • bl32_ep.pc = 0x260100000

You can’t set the pc/link address of the bl32 kernel/TOS to be right at the start of the tzdram because it will be partially overwritten.

The final steps are to build the ARM-TF BL31, and create the combined TOS.img using the provided python tool gen_tos_part_img.py, then to flash just the secure OS partition with just this image:

sudo ./flash.sh -k secure-os --image path-to-tos.img jetson-tx2 mmcblk0p1