Initiating data transfer from Endpoint to RC

Hi,
My setup is like one jetson-xavier acts as RC and another jetson-xavier acts as EP.
I want to transfer data from endpoint driver(pci-epf-nv-test.c).

To achieve that i have reserved 0x200000 bytes of memory starting from 0xe0000000 in RC side.

In EP side i make use of pci_epc_mem_alloc_addr,pci_epc_map_addr(here mapped 0xe0000000 as pci address) and initiated a data transfer by writing at virtual address returned by pci_epc_mem_alloc_addr.

But in RC side i observed error: Unhandled context fault: iova=0xe0000000
Can you please help us ? Am i doing anything wrong here?
Should i have to do address translation for inbound in RC?

After disabling smmu, i can able to achieve it.
To disable smmu , removed iommus and dma-coherent form device tree file for pcie5

And set all McSidStreamidOverrideConfigPcie5* to 0x0000007f in bootloader/t186ref/BCT/tegra194-memcfg-sw-override.cfg

referred:pcie smmu issue

How is this done? Since the SMMU is enabled on the RP side also, we have to use memory allocations APIs like dma_alloc_coherent() and since they don’t reserve the memory that we want (like 0xe0000000), I’m wondering how is it done. The fact that we have observed “Unhandled context fault: iova=0xe0000000” error means that this allocations is not in the records of SMMU hence it has thrown error when it saw access coming to this address from PCIe.

@vidyas To initiate the transfer from EP side, i have used the address returned by dma_alloc_coherent used at RP side.
The dma address which i get from dma_alloc_coherent is 0xffffe000. For that same address, i have initiated transfer from EP side.
But I’m receiving Unhandled context fault: smmu0, iova=0xffff0000.

Why the received address is different?

Note:above thing i tried by enabling smmu

are you setting up any iATU outbound region in the EP side?

No i have not. But this issue resolved when set the dma mask to 0xffff0000.
Do you know why this is happening?

I have additional question.
Is it possible to access RC side from the EP side without opening outbound iATU region on the EP side and inbound iATU region on the CR side?

If you are referring to accessing the RP side from the EP side using EP’s CPU, then, No.
But, if EPs DMA engine can be used, then, RP’s system memory can be set as a target and initiate transfers for which there is no need to program EP’s iATU outbound regions.

OK, Thanks.

I understood that the only way to access RP from EP without driver modification is to run DMA from EP to RP.