Hi,everyone!
We have created a lattice LCMXO2-4000HC-6BG256C cpld board as parallel to mipi csi bridge,but we failed interface it to JTK1 CSIA.More details below:
- We have successfully interfaced ov5640 to jtk1 csia,the output of ov5640 is 1080p@30Hz with yuv422 format.Two data lanes are occupied to tx and rx those image data.
- lattice cpld firmware is generated from reference diamond project below:
http://www.latticesemi.com/FileExplorer.aspx?media={D95C3FAF-41B2-483D-9D4E-5AB4D6D81C73}&document_id=51373
we just set the clock lane to continuous mode.(default is discontinuous) - We have verify the lattice csi tx with another lattice cpld flashed with csi rx firmware.The parallel output of csi rx is fine.
- Driver is modified from the driver of ov5640.
- We have created a virtual cam_i2c slave with verilog for camera detect and device register.
- Following is log info.
[ 9710.357450] vi vi.0: initialized
[ 9710.360653] platform vi.1: Driver vi requests probe deferral
[ 9710.360694] soc-camera-pdrv soc-camera-pdrv.3: Probing soc-camera-pdrv.3
[ 9710.480816] soc camper ov5640
[ 9710.491465] ov5640 2-003c: Chip ID 0x0000
[ 9710.495433] vi vi.1: initialized
[ 9710.500962] vi vi.0: Supporting mbus format code 0x2006 using YUV422 (UYVY) packed
[ 9710.500969] vi vi.0: Supporting mbus format code 0x2006 using YUV422 (VYUY) packed
[ 9710.500973] vi vi.0: Supporting mbus format code 0x2006 using YUV422 (YUYV) packed
[ 9710.500976] vi vi.0: Supporting mbus format code 0x2006 using YUV422 (YVYU) packed
[ 9710.500979] vi vi.0: Supporting mbus format code 0x2006 using YUV420 (YU12) planar
[ 9710.500983] vi vi.0: Supporting mbus format code 0x2006 using YVU420 (YV12) planar
[ 9710.502626] soc-camera-pdrv soc-camera-pdrv.1: Probing soc-camera-pdrv.1
[ 9710.502651] vi vi.0: Tegra camera driver loaded.
[ 9710.515432] vi vi.1: Supporting mbus format code 0x100e using RGBA 8-8-8-8
[ 9710.516915] vi vi.1: Tegra camera driver loaded.
[ 9710.518360] ov5640_s_power ::1
[ 9710.518527] ov5640_s_power ::0
[ 9715.270583] ov5640_s_power ::1
[ 9715.283031] ov5640_s_stream 1111
[ 9715.283046] mv ov5640 stream on
[ 9715.283164] tegra-i2c tegra12-i2c.2: no acknowledge from address 0x3c
[ 9715.283258] ov5640 2-003c: ov5840: i2c transfer failed, addr: 0, value: 01
[ 9715.293315] init 0x09================
[ 9715.493533] vi vi.0: CSI_A syncpt timeout, syncpt = 1, err = -11
[ 9715.501637] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
[ 9715.508003] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 9715.515988] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 9715.521363] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 9715.526330] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 9715.531154] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 9715.535987] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 9715.541169] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 9715.546865] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 9715.552449] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 9715.557311] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 9715.761647] vi vi.0: CSI_A syncpt timeout, syncpt = 2, err = -11
[ 9715.768932] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
[ 9715.774393] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 9715.780668] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 9715.786125] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 9715.791115] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 9715.795998] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 9715.800817] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 9715.805835] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 9715.815261] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 9715.821288] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 9715.826223] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 9716.030445] vi vi.0: CSI_A syncpt timeout, syncpt = 3, err = -11
[ 9716.037740] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
[ 9716.042835] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 9716.047731] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 9716.052534] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 9716.057370] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 9716.062193] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 9716.067538] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 9716.072448] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 9716.077997] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 9716.083622] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 9716.088509] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 9716.293526] vi vi.0: CSI_A syncpt timeout, syncpt = 4, err = -11
[ 9716.301157] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
[ 9716.306640] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 9716.312264] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 9716.317063] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 9716.321912] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 9716.326891] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 9716.331757] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 9716.336672] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 9716.342258] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 9716.348071] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 9716.353074] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 9716.557438] vi vi.0: CSI_A syncpt timeout, syncpt = 5, err = -11
[ 9716.564687] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
[ 9716.570497] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 9716.575909] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 9716.580645] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 9716.585459] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 9716.590547] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 9716.595737] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 9716.600649] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 9716.606206] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 9716.611976] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 9716.619366] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 9716.825460] vi vi.0: CSI_A syncpt timeout, syncpt = 6, err = -11
[ 9716.832175] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
[ 9716.836932] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 9716.842093] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 9716.846888] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 9716.851748] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 9716.856627] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 9716.861551] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 9716.866331] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 9716.871938] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 9716.877750] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 9716.882674] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 9717.087580] vi vi.0: CSI_A syncpt timeout, syncpt = 7, err = -11
[ 9717.095435] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
[ 9717.100989] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 9717.105875] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 9717.110607] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 9717.115499] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 9717.120488] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 9717.125372] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 9717.130142] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 9717.136021] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 9717.141601] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 9717.146544] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 9717.351538] vi vi.0: CSI_A syncpt timeout, syncpt = 8, err = -11
[ 9717.358941] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
[ 9717.364355] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 9717.369419] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 9717.374167] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 9717.379268] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 9717.384243] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 9717.389071] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 9717.393845] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 9717.399432] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 9717.405153] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 9717.410082] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 9717.614445] vi vi.0: CSI_A syncpt timeout, syncpt = 9, err = -11
[ 9717.622106] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
[ 9717.627603] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 9717.632481] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 9717.637276] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 9717.642095] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 9717.647067] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 9717.651839] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 9717.656752] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 9717.662600] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 9717.668177] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 9717.673140] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 9717.877325] vi vi.0: CSI_A syncpt timeout, syncpt = 10, err = -11
[ 9717.883693] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
[ 9717.888588] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[ 9717.893431] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[ 9717.898246] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[ 9717.903081] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 9717.908025] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 9717.913188] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 9717.918077] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 9717.923690] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 9717.929307] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 9717.934289] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[ 9717.956308] init 0x09================
[ 9718.156604] ov5640_s_stream 1111
[ 9718.156647] mv ov5640 stream off
[ 9718.156886] tegra-i2c tegra12-i2c.2: no acknowledge from address 0x3c
[ 9718.157042] ov5640 2-003c: ov5840: i2c transfer failed, addr: 0, value: 00
[ 9718.173889] ov5640_s_power ::0
- Pls let me know if you need more details.
Does anyone have done this successfully?
Any ideas about what is wrong with my situation? Appreciate it.
Thank you!!