Interpret debug trace log : PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000080

@ShaneCCC

This MIPI bus refers to FPGA sensor output signal?

Also:

When i change the CIL settle time , i get the PHY_INTR0 error which means there is an issue with CIL settle time.
This makes it clear the cil_settletime=0 is ideal for us.

When the cil_settletime = 0
we get VIFALC_TDSTATE which might mean MIPI bus has no data.

The cil_settletime = 0; tell the NVCSI driver calculate the settle time base on pix_clk_hz.

@ShaneCCC

The pix_clk_hz is 80 MHz

Could you tell us where the problem might lie? We tried different pix clk hz and cil settle time
Yet we are unable to get video dump on Orin through FPGA.

[   52.431667] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 5000 ms
[   52.444405] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[   52.455145] (NULL device *): vi_capture_control_message: NULL VI channel received
[   52.473538] (NULL device *): vi_capture_control_message: NULL VI channel received
[   52.492010] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[  121.548715] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 5000 ms
[  121.561485] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[  121.572123] (NULL device *): vi_capture_control_message: NULL VI channel received
[  121.590550] (NULL device *): vi_capture_control_message: NULL VI channel received
[  121.609033] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[  127.692903] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 5000 ms
[  127.702075] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[  127.712144] (NULL device *): vi_capture_control_message: NULL VI channel received
[  127.730518] (NULL device *): vi_capture_control_message: NULL VI channel received
[  127.760694] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[  132.812980] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 5000 ms
[  132.822146] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[  132.832130] (NULL device *): vi_capture_control_message: NULL VI channel received
[  132.850501] (NULL device *): vi_capture_control_message: NULL VI channel received

We are able to probe the data signals as well

image

What’s the MIPI clocks?

Here is the MIPI-CSI CLK & DATA spec coming from FPGA - MIPI Clock is 287.5Mhz, datarate is 580Mbps, 2 datalines, Byte Clock is 71.875, Data Type YUV422_8

Did you try serdes_pix_clk_hz/pix_clk_hz = 575Mhz?

@ShaneCCC

We tried the 575MHz clock and we hit the same trace log:


  kworker/2:2-105     [002] ....   254.146924: rtcpu_vinotify_event: tstamp:8801214873 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:281628935520 data:0x759e300010000000
     kworker/2:2-105     [002] ....   254.146930: rtcpu_vinotify_event: tstamp:8801215143 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:281628941952 data:0x0000000031000001
     kworker/2:2-105     [002] ....   254.146930: rtcpu_vinotify_event: tstamp:8801215418 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:281629022592 data:0x759e2d0010000000
     kworker/2:2-105     [002] ....   254.146931: rtcpu_vinotify_event: tstamp:8801215638 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:281629029120 data:0x0000000031000002
     kworker/2:2-105     [002] ....   259.530847: rtcpu_vinotify_event: tstamp:8968843504 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:286991794944 data:0x759e300010000000
     kworker/2:2-105     [002] ....   259.530850: rtcpu_vinotify_event: tstamp:8968843643 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:286991837632 data:0x0000000031000001
     kworker/2:2-105     [002] ....   260.258835: rtcpu_vinotify_event: tstamp:8992172887 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:287737628704 data:0x759e2d0010000000
     kworker/2:2-105     [002] ....   260.258838: rtcpu_vinotify_event: tstamp:8992173028 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:287737672032 data:0x0000000031000002
     kworker/2:2-105     [002] ....   264.742766: rtcpu_vinotify_event: tstamp:9131604955 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:292200988128 data:0x759e300010000000
     kworker/2:2-105     [002] ....   264.742770: rtcpu_vinotify_event: tstamp:9131605095 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:292201030816 data:0x0000000031000001
     kworker/2:2-105     [002] ....   265.694753: rtcpu_vinotify_event: tstamp:9161445248 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:293159489120 data:0x759e2d0010000000
     kworker/2:2-105     [002] ....   265.694757: rtcpu_vinotify_event: tstamp:9161445388 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:293159532480 data:0x0000000031000002
     kworker/2:2-105     [002] ....   269.846690: rtcpu_vinotify_event: tstamp:9291654335 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:297320444896 data:0x759e300010000000
     kworker/2:2-105     [002] ....   269.846694: rtcpu_vinotify_event: tstamp:9291654501 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:297320487552 data:0x0000000031000001
     kworker/2:2-105     [002] ....   270.966705: rtcpu_vinotify_event: tstamp:9325556564 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:298417678336 data:0x759e2d0010000000
     kworker/2:2-105     [002] ....   270.966709: rtcpu_vinotify_event: tstamp:9325556703 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:298417721696 data:0x0000000031000002

Looks like doesn’t receive any validate from MIPI bus.
Suppose it could be hardware or sensor timing or initial sequency problem.