This MIPI bus refers to FPGA sensor output signal?
Also:
When i change the CIL settle time , i get the PHY_INTR0 error which means there is an issue with CIL settle time.
This makes it clear the cil_settletime=0 is ideal for us.
When the cil_settletime = 0
we get VIFALC_TDSTATE which might mean MIPI bus has no data.
The cil_settletime = 0; tell the NVCSI driver calculate the settle time base on pix_clk_hz.
The pix_clk_hz is 80 MHz
Could you tell us where the problem might lie? We tried different pix clk hz and cil settle time
Yet we are unable to get video dump on Orin through FPGA.
[ 52.431667] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 5000 ms
[ 52.444405] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[ 52.455145] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 52.473538] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 52.492010] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[ 121.548715] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 5000 ms
[ 121.561485] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[ 121.572123] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 121.590550] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 121.609033] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[ 127.692903] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 5000 ms
[ 127.702075] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[ 127.712144] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 127.730518] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 127.760694] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[ 132.812980] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 5000 ms
[ 132.822146] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[ 132.832130] (NULL device *): vi_capture_control_message: NULL VI channel received
[ 132.850501] (NULL device *): vi_capture_control_message: NULL VI channel received
We are able to probe the data signals as well
What’s the MIPI clocks?
Here is the MIPI-CSI CLK & DATA spec coming from FPGA - MIPI Clock is 287.5Mhz, datarate is 580Mbps, 2 datalines, Byte Clock is 71.875, Data Type YUV422_8
Did you try serdes_pix_clk_hz/pix_clk_hz = 575Mhz?
We tried the 575MHz clock and we hit the same trace log:
kworker/2:2-105 [002] .... 254.146924: rtcpu_vinotify_event: tstamp:8801214873 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:281628935520 data:0x759e300010000000
kworker/2:2-105 [002] .... 254.146930: rtcpu_vinotify_event: tstamp:8801215143 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:281628941952 data:0x0000000031000001
kworker/2:2-105 [002] .... 254.146930: rtcpu_vinotify_event: tstamp:8801215418 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:281629022592 data:0x759e2d0010000000
kworker/2:2-105 [002] .... 254.146931: rtcpu_vinotify_event: tstamp:8801215638 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:281629029120 data:0x0000000031000002
kworker/2:2-105 [002] .... 259.530847: rtcpu_vinotify_event: tstamp:8968843504 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:286991794944 data:0x759e300010000000
kworker/2:2-105 [002] .... 259.530850: rtcpu_vinotify_event: tstamp:8968843643 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:286991837632 data:0x0000000031000001
kworker/2:2-105 [002] .... 260.258835: rtcpu_vinotify_event: tstamp:8992172887 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:287737628704 data:0x759e2d0010000000
kworker/2:2-105 [002] .... 260.258838: rtcpu_vinotify_event: tstamp:8992173028 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:287737672032 data:0x0000000031000002
kworker/2:2-105 [002] .... 264.742766: rtcpu_vinotify_event: tstamp:9131604955 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:292200988128 data:0x759e300010000000
kworker/2:2-105 [002] .... 264.742770: rtcpu_vinotify_event: tstamp:9131605095 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:292201030816 data:0x0000000031000001
kworker/2:2-105 [002] .... 265.694753: rtcpu_vinotify_event: tstamp:9161445248 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:293159489120 data:0x759e2d0010000000
kworker/2:2-105 [002] .... 265.694757: rtcpu_vinotify_event: tstamp:9161445388 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:293159532480 data:0x0000000031000002
kworker/2:2-105 [002] .... 269.846690: rtcpu_vinotify_event: tstamp:9291654335 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:297320444896 data:0x759e300010000000
kworker/2:2-105 [002] .... 269.846694: rtcpu_vinotify_event: tstamp:9291654501 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:297320487552 data:0x0000000031000001
kworker/2:2-105 [002] .... 270.966705: rtcpu_vinotify_event: tstamp:9325556564 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:298417678336 data:0x759e2d0010000000
kworker/2:2-105 [002] .... 270.966709: rtcpu_vinotify_event: tstamp:9325556703 cch:0 vi:1 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:298417721696 data:0x0000000031000002
Looks like doesn’t receive any validate from MIPI bus.
Suppose it could be hardware or sensor timing or initial sequency problem.
How do we debug sensor timing and sequence issue given that all the above steps have been tried.
Maybe checking with sensor vendor to confirm the timing that follow the MIPI spec.
Thanks
MIPI output from the Lattice crosslink FPGA has two data lanes of 8 bit each (yuv422). What would be the csi_pixel_bit_depth in the device tree?
YUV422 8 bit should be 16 for the csi_pixel_bit_depth
What does this mean?
kworker/2:3-393 [002] .... 64.588306: rtcpu_vinotify_event: tstamp:2896422542 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:92669172448 data:0x759d580010000000
kworker/2:3-393 [002] .... 64.588309: rtcpu_vinotify_event: tstamp:2896422678 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:92669178880 data:0x0000000031000001
kworker/2:3-393 [002] .... 64.588310: rtcpu_vinotify_event: tstamp:2896422832 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:92669234528 data:0x759d550010000000
kworker/2:3-393 [002] .... 64.588310: rtcpu_vinotify_event: tstamp:2896422965 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:92669241088 data:0x0000000031000002
kworker/2:3-393 [002] .... 69.688309: rtcpu_vinotify_event: tstamp:3055930129 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:97773136352 data:0x759d580010000000
kworker/2:3-393 [002] .... 69.688312: rtcpu_vinotify_event: tstamp:3055930265 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:97773179040 data:0x0000000031000001
kworker/2:3-393 [002] .... 69.800319: rtcpu_vinotify_event: tstamp:3059727799 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:97904353536 data:0x759d550010000000
kworker/2:3-393 [002] .... 69.800321: rtcpu_vinotify_event: tstamp:3059727936 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:97904396864 data:0x0000000031000002
DATA SIGNAL.zip (627.1 KB)
Hello Shane,
Attached is the screen shot of CSI data sequence and timing parameters. We get " rtcpu_nvcsi_intr: tstamp:4501871730 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000004 " most of the time CIL is set to “0”. We tried manually changing CIL time from 1ns to 20ns, the error is mostly “class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x10000000” along with “status:0x00000004”
We also tried configuring a Lattice Crosslink FPGA as DHPY RX and received the signals sent from DPHY TX of another Lattice Crosslink FPGA signals and we are able to see all the all the MIPI-CSI data along with packet header. We also see SOT information as expected. Please go through the attached screenshots of the CSI data lane and please verify timing parameters.
Please suggest any changes that we can try!
Thanks,
Tell the SOT multiple bits error. Could be the settle time cause the problem.
Set the CIL settle to 0 and confirm the pix_clk_hz due to the ths_settle is calculated depend on pix_clk_hz.
Keeping cil_settletime = 0 , we have tried changing the pix_clk_hz = 80Mhz, 72MHz, 46MHz, 144MHz.
we encounter the same error:
PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000004
could u please check the attached data signals that we get and confirm on ur end?
Hi,
We are able to get the video on CSI -1 after changing some IP core settings and replacing the Orin SOM.
When we try to ingest on CSI - 3 we get the VIFALC_TDSTATE error, and this error is constant it does not change at all even when changes are made to the device tree.
Please assist.
This doesn’t mean error.
What’s the full trace for CSI-3?
