Is it possible to limit HDMI2.1 to 2.0?

Autonomous Machines Jetson & Embedded Systems Jetson Orin NX
1

Hi NV,
cause of some reason,
we would like to limit HDMI2.1 to HDMI2.0,
is it possible to achieve by SW modification?
thanks.

4

Hi,

Is the development already starting or you are just checking and doing evaluation?

5

Hi Wayne,
we are checking and doing evaluation,
but very likely need to do that cause of HW limitation,
thanks.

6

Hi,

We have below questions here to understand the problem.

  1. By limiting to HDMI 2.0, is it because you don’t want HDMI 2.1 TMDS or HDMI 2.1 FRL?
  2. What exactly is the limitation from your side to limit to HDMI 2.0 ? Is it wrt your platform or sinks(monitors) you use?
7

Hi Wayne,
the HDMI connector and HDMI re-timer on our carrier board just support HDMI 2.0,
I think HDMI 2.1 TMDS/FLR doesn’t support either,
thanks.

8

Hi~Wayne,
Since our HDMI re-timer only supports 6Gbps per channel of TMDS signal, Can we just disable HDMI 2.1 FRL function on Jetson Orin NX/Nano module??

Thx

9

Hi~Wayne,
Sorry to bother you. Is there any update?

Thx

10

Hi Ken,

This is still under internal discussion.

11

Hi~Wayne,
Do you get the result after an internal discussion?

Thx

12

Hi Ken,

Sorry for late reply. There won’t be official solution for this but just some workaround.

The workaround is to limit the display pixel clock to 600MHz.

13

Hi Wayne,
do you mean limit “HDMI” display pixel clock to 600MHz?
any risk for the workaround?
could you give us patch?
thanks.

14

Hi,

It does not have side effect at this moment. The you need to adjust this max rate in bpmp dtb to 600Mhz.

And bpmp dtb is not in public source so you need to convert it from binary by using dtc tool.

        clock@nvdisplay_disp {

         clk-id = <TEGRA234_CLK_DISP>;

          max-rate-maxn = <0 1191000000>;

        };

        clock@vpll0 {

          clk-id = <TEGRA234_CLK_VPLL0>;

          max-rate-maxn = <0 1191000000>;

        };

        clock@vpll1 {

          clk-id = <TEGRA234_CLK_VPLL1>;

          max-rate-maxn = <0 1191000000>;

       };
15

Hi Wayne,
which one need to modify?
clock@nvdisplay_disp, clock@vpll0, clock@vpll1?
or all of them?
thanks.

16

This one.

17

Hi Wayne,
how to verify the modification is correct?
thanks.

19

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