Is it possible to set MCLK to a frequency other than 24MHz?

[user98878]

Hello.
I am developing a driver for a multi csi-2 camera on AGX Xavier.

Referring to the following two dtsi:
tegra194-p2822-0000-camera-imx390-a00.dtsi
tegra194-camera-imx390-a00.dtsi
I set my clock settings like this:
mycam0 : mycam@xx {
:
mclk = “extperiph1”;
:
mode0 {
mclk_khz = “18048”;
:

But the actual output frequency was about 18.5MHz.
How do I set it to get 18.048MHz MLCK?

Thanks,
maejun as user98878

[ShaneCCC]

The extperiph1 parent is pllp_out0(408000000) and the divider’s scaler is 0.5
And the output clock only able generate as near as request.

[user98878]

Thank you for your quick answer.
Is the divider’s scaler fixed to 0.5?
Is there a way to get the exact 18.048MHz clock from Xavier’s CSI connector?

[ShaneCCC]

Yes, the scaler fixed to 0.5

[user98878]

OK. thank you.
Is there any other way to get a clock closer to 18.048MHz from a pin on the Xavier’s CSI connector?

[ShaneCCC]

Check others clock source from the /sys/kernel/debug/clk/clk_sumary to check if able get that clock.

[user98878]

After all, 18.5454MHz is likely to be acceptable.
Thank you very much for your help.