Is there a maximum VDD_IN to POWER_EN delay time, and what is the VIH of the POWER_EN input?

On our custom board, we are using a button controller IC to keep all the supplies powered off until the power button is pressed. This button controller IC replaces the Module Power On/Off logic on page 13 of the carrier board reference design. In the first revision of the board, we missed including the asymmetric delay that adds a 470ms RC time constant to the rising edge of the POWER_EN signal, so I have been working on a rework that can satisfy the requirement to have at least 400ms delay between VDD_IN being present and the POWER_EN input going high. In the process, I have made some observations that suggest that the POWER_EN input has a VIH level exceeding 82% of VDD_IN, and that making the POWER_EN delay (or rise time) too large can also cause problems.

In our custom board, the POWER_EN input of the Nano is connected to the power good output of the switching regulator that powers the Nano. This an open drain output that only has a 25us delay between output power being valid and the open drain output being tri-stated. I started with a 10K pullup on the POWER_EN signal and no capacitor and found that multiple boards would intermittently be in a state where the Jetson Nano would not finish powering up, as evidenced by SYS_RST remaining low. This behavior was not observed on all boards, and the behavior would come and go.

After reviewing the design guide and seeing that we missed implementing the 400ms delay from VDD_IN to POWER_EN, I began experimenting with different pullup resistors on POWER_EN and different capacitors from POWER_EN to GND. Because of the 100K pulldown on POWER_EN inside the Nano, there is a limit on how much I could increase the pullup resistor to increase the RC time constant on the rising edge of POWER_EN. With only a 22K pullup resistor, and confirmation of 4.1V on the POWER_EN signal, the Jetson Nano was not powering up. Believing this to be evidence of a high VIH level on POWER_EN, and having observed intermittent issues with a 10K pullup resistor, I reduced the pullup resistor to 6.8K.

I then added 20uF (2x 10uF ceramic caps) from POWER_EN to GND. Although the time constant of 6.8K and 20uF is only 136ms, the Jetson Nano was consistently powering up. I then added 3 more 10uF caps for a total of 50uF to move the RC time constant closer to the reference design. With 6.8K and 50uF, the Jetson Nano again did not power up, even though I confirmed that the POWER_EN signal reached a level of 4.65V, which should be well above the VIH level of the POWER_EN input.

If the VIH of POWER_EN is high (e.g. 4.2V), then a 6.8K pullup and 50uF capacitance takes over 600ms to cross the trip point. Is a 600ms delay a problem, or is the slow rise time on POWER_EN a problem? I haven’t seen any guidance against having too long of a delay from VDD_IN to POWER_EN high or against having too slow of a slew rate.

Hi, I don’t think such adding pull-up to POWER_EN is good solution. It could cause lower voltage level and too long rising time which is not validated and could have potential risks. You can refer to ON/OFF logia design in P3449, to use a RC (R377 and C280) + buffer for this.

When we spin the board, we will add a buffer for the POWER_EN input. For now, though, I am trying to get the prototypes to work reliably (enough) to verify the rest of the design. According to the design guide “POWER_EN is routed to a Schmitt trigger buffer on the module. A 100kΩ pulldown is also on the module.” What is the VIH level of this Schmitt trigger? I haven’t found this specified anywhere.

A Schmitt trigger is usually effective at squaring up signals with long rise times, but I have found that having too much capacitance on the POWER_EN line prevents the Nano from powering up properly. If the slew rate is the issue, as you suggest, is there a maximum slew rate specification?

Hi, the Schmitt trigger is 74LVC2G17GW, you need to get its spec online as we can’t share that.

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