Hi experts,
I’m thinking that I’m having issues with the chip select signal (using SPI on the J21 header) where only the first request will be answered by my device. If I disconnect the CS wire (pin 26 on the J21 header, CS1) and reconnect it (going from low to undefined to low), seems like is enough to get the device to answer. But it seems as though when the communication is over, it isn’t going back to high (I assume 3.3v), I don’t yet have a signal analyzer.
Here’s what the relevant section of the device tree file looks like :
spi@3240000 {
reg = <0x0 0x3240000 0x0 0x10000>;
dmas = <0x19 0x12 0x19 0x12>;
interrupts = <0x0 0x27 0x4>;
compatible = "nvidia,tegra186-spi";
clock-names = "spi", "pll_p", "clk_m";
reset-names = "spi";
clocks = <0xd 0x4a 0xd 0x10d 0xd 0x261>;
spi-max-frequency = <500000>;
nvidia,dma-request-selector = <0x19 0x12>;
resets = <0xd 0x2b>;
status = "okay";
#address-cells = <0x1>;
phandle = <0x7d>;
nvidia,clk-parents = "pll_p", "clk_m";
#stream-id-cells = <0x1>;
#size-cells = <0x0>;
dma-names = "rx", "tx";
linux,phandle = <0x7d>;
spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <500000>;
#io-channel-cells = <0x1>;
nvidia,cs-inactive-cycles = <0x1>;
nvidia,enable-hw-based-cs;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
Is there something I overlooked? I’ve seen someone with a similar problem on another thread… can’t find it now. But I’ve seen references to using nvidia,chipselect-gpio instead of enable-hw-based-cs. I’ve also seen all the nvidia,* settings under a controller child node on some other thread too.
Any help/guidance appreciated!