Issue with CS signal

Hi experts,
I’m thinking that I’m having issues with the chip select signal (using SPI on the J21 header) where only the first request will be answered by my device. If I disconnect the CS wire (pin 26 on the J21 header, CS1) and reconnect it (going from low to undefined to low), seems like is enough to get the device to answer. But it seems as though when the communication is over, it isn’t going back to high (I assume 3.3v), I don’t yet have a signal analyzer.

Here’s what the relevant section of the device tree file looks like :

spi@3240000 {
                reg = <0x0 0x3240000 0x0 0x10000>;
                dmas = <0x19 0x12 0x19 0x12>;
                interrupts = <0x0 0x27 0x4>;
                compatible = "nvidia,tegra186-spi";
                clock-names = "spi", "pll_p", "clk_m";
                reset-names = "spi";
                clocks = <0xd 0x4a 0xd 0x10d 0xd 0x261>;
                spi-max-frequency = <500000>;
                nvidia,dma-request-selector = <0x19 0x12>;
                resets = <0xd 0x2b>;
                status = "okay";
                #address-cells = <0x1>;
                phandle = <0x7d>;
                nvidia,clk-parents = "pll_p", "clk_m";
                #stream-id-cells = <0x1>;
                #size-cells = <0x0>;
                dma-names = "rx", "tx";
                linux,phandle = <0x7d>;
                spi@1 {
                                  compatible = "spidev";
                                  reg = <1>;
                                  spi-max-frequency = <500000>;
                                  #io-channel-cells = <0x1>;
                                  nvidia,cs-inactive-cycles = <0x1>;
                                  nvidia,enable-hw-based-cs;
                                  nvidia,cs-setup-clk-count = <0x1e>;
                                  nvidia,cs-hold-clk-count = <0x1e>;
                                  nvidia,rx-clk-tap-delay = <0x1f>;
                                  nvidia,tx-clk-tap-delay = <0x0>;
                };
        };

Is there something I overlooked? I’ve seen someone with a similar problem on another thread… can’t find it now. But I’ve seen references to using nvidia,chipselect-gpio instead of enable-hw-based-cs. I’ve also seen all the nvidia,* settings under a controller child node on some other thread too.

Any help/guidance appreciated!

So I was able to make some progress on my issue and it seems by now that I can get SPI3.0 working but not SPI3.1. The CS pin on the J21 header (pin 24) will go low when communications take place, but not pin 26 as I would like. And editing the dts file to use spi@1 versus spi@0 won’t work either. And my existing hardware has that pin wired for that function so ideally I figure this out.

It might be doable with working on pinmux, but I really don’t have the right understanding just yet of how to properly use the pinmux Excel spreadsheet. I’m trying and learning but I’m starting to think this is not doable.

For my application one of these would solve the issue :

  1. redirect CS0 to CS1 (the actual physical pin). Can I do that from the device tree? From the tx2 pinout (https://www.jetsonhacks.com/nvidia-jetson-tx2-j21-header-pinout/), pin26 doesn’t seem to be connected to gpio unlike some other pins (pin24 for instance). Can i fix that somehow from the device tree or is this physically not connected period? The pinout suggests CS1…
  2. redirect SPI2 that has the CS0 and CS1 (preferred solution) on J21. Again, how do I do that?

thanks…

spi-client device controller properties:
Below properties should be defined under ‘controller-data’ child node

  • nvidia,enable-hw-based-cs : (Boolean) Use the HW based CS if enabled.
spi@1 {
                                  compatible = "spidev";
                                  reg = <1>;
                                  spi-max-frequency = <500000>;
                                  #io-channel-cells = <0x1>;
                                  controller-data {
                                      nvidia,cs-inactive-cycles = <0x1>;
                                      nvidia,enable-hw-based-cs;
                                      nvidia,cs-setup-clk-count = <0x1e>;
                                      nvidia,cs-hold-clk-count = <0x1e>;
                                      nvidia,rx-clk-tap-delay = <0x1f>;
                                      nvidia,tx-clk-tap-delay = <0x0>;
                                  }
                };

Thanks @ShaneCCC ! Is this supposed to get the signal active on spi CS1 (CS0)? It’s there in the config, the system sees it but somehow the signal doesn’t seem to go low on CS1 when it’s called. I didn’t try yet to see with a signal analyzer - will probably do later in the week - but want to make sure I’m not trying to do something that is undoable.