Issue with transferring video frames through dma channel_1 in Jetson AGX Xavier board

Hi,
We have configured the Jetson AGX Xavier boards as PCI endpoint and root complex and tried to transfer video frames from endpoint to root complex using endpoint dma channels.
When we transferred video frames from endpoint using dma channel_0, it got streamed on the root complex without any issue but, when we tried to transfer video frames through dma channel_1, the stream got freeze on a frame after streaming for some time. when we try to stream again, we did not get any data from endpoint. This issue was not there, when we used dma channel_0. can you tell me, what may be the reason for this issue?

Sorry for the late response, is this still an issue to support? Thanks

All PCIe DMA channels are verified in our internal testing.
Please share your PCIe DMA source code for review.

int config_dma_poll(struct pci_epf_test_camera *pd, u64 src,u64 dst, u32 size, int channel)
{
u32 val;
int count = 100000;
u64 start_time_ns;
int flag =0x10001;

// printk(“config_dma_poll src:%llx,dst:%llx,size:%x\n”,src,dst,size);
/* program registers /
/
Enable Write Engine */
dma_common_wr(pd->dma_base, DMA_WRITE_ENGINE_EN_OFF_ENABLE,
DMA_WRITE_ENGINE_EN_OFF);

        /* Un Mask DONE and ABORT interrupts */
    val = dma_common_rd(pd->dma_base, DMA_WRITE_INT_MASK_OFF);
    val &= ~(1 << channel);             /* DONE */
    val &= ~(1 << ((channel) + 16));    /* ABORT */
    dma_common_wr(pd->dma_base, val, DMA_WRITE_INT_MASK_OFF);


val = dma_channel_rd(pd->dma_base, channel,
                         DMA_CH_CONTROL1_OFF_WRCH);

val = DMA_CH_CONTROL1_OFF_WRCH_LIE;
    dma_channel_wr(pd->dma_base, channel, val,
                   DMA_CH_CONTROL1_OFF_WRCH);


dma_channel_wr(pd->dma_base, channel, size,
                   DMA_TRANSFER_SIZE_OFF_WRCH);

    dma_channel_wr(pd->dma_base, channel,
                   (src & 0xFFFFFFFF),
                   DMA_SAR_LOW_OFF_WRCH);
    dma_channel_wr(pd->dma_base, channel,
                   ((src >> 32) & 0xFFFFFFFF),
                   DMA_SAR_HIGH_OFF_WRCH);

    dma_channel_wr(pd->dma_base, channel,
                   (dst & 0xFFFFFFFF),
                   DMA_DAR_LOW_OFF_WRCH);
    dma_channel_wr(pd->dma_base, channel,
                   ((dst >> 32) & 0xFFFFFFFF),
                   DMA_DAR_HIGH_OFF_WRCH);

start_time_ns = ktime_get_ns();

 /* start DMA (ring the door bell) */
    /* ring the door bell with channel number */
    dma_common_wr(pd->dma_base, channel,
                  DMA_WRITE_DOORBELL_OFF);



//poll
while(count--)
{
	val = dma_common_rd(pd->dma_base, DMA_WRITE_INT_STATUS_OFF);
	if(val & (flag<<channel) )
	{
		printk("time taken %llx\n",ktime_get_ns() - start_time_ns);
		dma_common_wr(pd->dma_base, 0x10001, DMA_WRITE_INT_CLEAR_OFF);

// printk(“test_camera packet transferred from DMA with count:%d\n”,count);
break;
}
}

return 0;

}

I’ve shared my source code to transfer data using dma channels. While using dma channel_0 there was no issue but, I’m facing issue while using channel_1.

Hi,

Need a minor fix, however I don’t think it is the root cause for the issue.

-dma_common_wr(pd->dma_base, 0x10001, DMA_WRITE_INT_CLEAR_OFF);
+dma_common_wr(pd->dma_base, (flag<<channel), DMA_WRITE_INT_CLEAR_OFF);

Dump below registers using “busybox devmem” when u observe the issue.

0x3a06004c
0x3a060054
0x3a060400
0x3a060408
0x3a06040c
0x3a060410
0x3a060414
0x3a060418

Thanks,
Manikanta

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