Issues with Jetson Nano Production and Jetson-io (and jetpack 4.6 rev1)

That patch won’t fixed the jetson-io problem. But fixed the GPIO pin configure. Did you apply the kernel patch also?

I haven’t had a chance to cross compile the new kernel and load it yet as I’ve been busy attending to other things, although my understanding is that it was just changing the GPIO registers, but I could fix that with busybox devmem . Also, as I tried to take another look at the dtc I ran into another error that would lock up the nano
[ 29.019307] nvgpu: 57000000.gpu nvgpu_set_error_notifier_locked:137 [ERR] error notifier set to 8 for ch 507
As the nano locked up, I was unable to pull the dmesg/kmsg. I can make it enter recovery mode and reflash it, however.

Is there a timeline on the jetson-io fix? Applying kernel patches and modifying the dts manually seems like a lot of fiddling just to get something as simple as an SPI interface up. Is there an image of a working jetson production eMMC w/ SPI available?

Is your Nano emmc version?
Other’s version without problem to configure by jetson-io.

Yes, as i’ve said before, this is the production eMMC version of the nano. If jetson-io doesn’t work with it, when will this be fixed?

And again, is there an image with functional SPI available for this product?

And yes, I know that jetson-io works for the dev nanos, because that’s what I’ve been using until now and the same code works fine with SPI. That’s how I know the problem is the production nanos.

To be more clear, the product is p3448-0002, as far as I can tell.

Any update @ShaneCCC to the jetson-io situation for the eMMC production Nano Modules? I should have time tomorrow to try recompiling the kernel, but I’d rather just have the jetson-io tools work.

Sorry, I don’t have device on hand to check this week. Will check it next week.

Any update to share @ShaneCCC ?

Apply below patch and replace the tegra210-p3448-0002-p3449-0000-b00.dtb at …/Linux_for_Tegra/kernel/dtb/ and reflash the device by below command.

sudo ./flash jetson-nano-devkit-emmc mmcblk0p1

diff --git a/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi b/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi
index ac8bda8..a6f455b 100644
--- a/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi
+++ b/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi
@@ -26,35 +26,13 @@

                gpio_default: default {
                        gpio-input = <
-                               TEGRA_GPIO(BB, 0)
-                               TEGRA_GPIO(B, 4)
-                               TEGRA_GPIO(B, 5)
-                               TEGRA_GPIO(B, 6)
-                               TEGRA_GPIO(B, 7)
-                               TEGRA_GPIO(DD, 0)
-                               TEGRA_GPIO(E, 6)
-                               TEGRA_GPIO(S, 5)
                                TEGRA_GPIO(A, 5)
                                TEGRA_GPIO(X, 4)
                                TEGRA_GPIO(X, 5)
                                TEGRA_GPIO(X, 6)
                                TEGRA_GPIO(Y, 1)
-                               TEGRA_GPIO(Y, 2)
-                               TEGRA_GPIO(V, 0)
                                TEGRA_GPIO(V, 1)
-                               TEGRA_GPIO(Z, 0)
                                TEGRA_GPIO(Z, 2)
-                               TEGRA_GPIO(J, 5)
-                               TEGRA_GPIO(J, 6)
-                               TEGRA_GPIO(J, 4)
-                               TEGRA_GPIO(J, 7)
-                               TEGRA_GPIO(G, 2)
-                               TEGRA_GPIO(G, 3)
-                               TEGRA_GPIO(C, 0)
-                               TEGRA_GPIO(C, 1)
-                               TEGRA_GPIO(C, 2)
-                               TEGRA_GPIO(C, 3)
-                               TEGRA_GPIO(C, 4)
                                TEGRA_GPIO(H, 2)
                                TEGRA_GPIO(H, 5)
                                TEGRA_GPIO(H, 6)

Applied the patch. Tried spidev_test, got nothing. Probed the pins, nothing.

Took a fresh dev module, jetson-io worked fine, SPI working.

Please provide a set of instructions to get a production jetson nano with eMMC to use SPI.

What’s the GPIO result?

sudo cat /sys/kernel/debug/tegra_gpio

On boot:

Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 A: 0:0 64 40 40 04 00 00 000000
 B: 0:1 f0 00 00 00 00 00 000000
 C: 0:2 1f 00 00 18 00 00 000000
 D: 0:3 00 00 00 00 00 00 000000
 E: 1:0 40 00 00 40 00 00 000000
 F: 1:1 00 00 00 00 00 00 000000
 G: 1:2 0c 00 00 00 00 00 000000
 H: 1:3 fd 99 00 60 00 00 000000
 I: 2:0 07 07 03 00 00 00 000000
 J: 2:1 f0 00 00 00 00 00 000000
 K: 2:2 00 00 00 00 00 00 000000
 L: 2:3 00 00 00 00 00 00 000000
 M: 3:0 00 00 00 00 00 00 000000
 N: 3:1 00 00 00 00 00 00 000000
 O: 3:2 00 00 00 00 00 00 000000
 P: 3:3 00 00 00 00 00 00 000000
 Q: 4:0 00 00 00 00 00 00 000000
 R: 4:1 00 00 00 00 00 00 000000
 S: 4:2 a0 80 00 20 00 00 000000
 T: 4:3 01 01 00 00 00 00 000000
 U: 5:0 00 00 00 00 00 00 000000
 V: 5:1 03 00 00 02 00 00 000000
 W: 5:2 00 00 00 00 00 00 000000
 X: 5:3 78 08 08 70 00 60 606000
 Y: 6:0 06 00 00 02 00 00 000000
 Z: 6:1 0f 08 00 05 00 04 000400
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 01 00 00 01 00 00 000000
CC: 7:0 92 80 80 10 00 12 121200
DD: 7:1 01 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000

With some devmem meddling:

 B: 0:1 00 00 00 00 00 00 000000
 C: 0:2 1f 00 00 18 00 00 000000
 D: 0:3 00 00 00 00 00 00 000000
 E: 1:0 40 00 00 40 00 00 000000
 F: 1:1 00 00 00 00 00 00 000000
 G: 1:2 0c 00 00 00 00 00 000000
 H: 1:3 fd 99 00 60 00 00 000000
 I: 2:0 07 07 03 00 00 00 000000
 J: 2:1 f0 00 00 00 00 00 000000
 K: 2:2 00 00 00 00 00 00 000000
 L: 2:3 00 00 00 00 00 00 000000
 M: 3:0 00 00 00 00 00 00 000000
 N: 3:1 00 00 00 00 00 00 000000
 O: 3:2 00 00 00 00 00 00 000000
 P: 3:3 00 00 00 00 00 00 000000
 Q: 4:0 00 00 00 00 00 00 000000
 R: 4:1 00 00 00 00 00 00 000000
 S: 4:2 a0 80 00 20 00 00 000000
 T: 4:3 01 01 00 00 00 00 000000
 U: 5:0 00 00 00 00 00 00 000000
 V: 5:1 03 00 00 02 00 00 000000
 W: 5:2 00 00 00 00 00 00 000000
 X: 5:3 78 08 08 70 00 60 606000
 Y: 6:0 06 00 00 02 00 00 000000
 Z: 6:1 0f 08 00 05 00 04 000400
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 01 00 00 01 00 00 000000
CC: 7:0 92 80 80 10 00 12 121200
DD: 7:1 01 00 00 01 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000

Neither works.

Looks like your device tree didn’t apply correct or your modification didn’t apply.

As I said before, I can solve the problem with devmem. But just for completeness sake, I applied the kernel patch pertaining to the gpio pin deallocation, I get this result:

Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 A: 0:0 64 40 40 04 00 00 000000
 B: 0:1 00 00 00 00 00 00 000000
 C: 0:2 00 00 00 00 00 00 000000
 D: 0:3 00 00 00 00 00 00 000000
 E: 1:0 00 00 00 00 00 00 000000
 F: 1:1 00 00 00 00 00 00 000000
 G: 1:2 00 00 00 00 00 00 000000
 H: 1:3 fd 99 00 60 00 00 000000
 I: 2:0 07 07 03 00 00 00 000000
 J: 2:1 00 00 00 00 00 00 000000
 K: 2:2 00 00 00 00 00 00 000000
 L: 2:3 00 00 00 00 00 00 000000
 M: 3:0 00 00 00 00 00 00 000000
 N: 3:1 00 00 00 00 00 00 000000
 O: 3:2 00 00 00 00 00 00 000000
 P: 3:3 00 00 00 00 00 00 000000
 Q: 4:0 00 00 00 00 00 00 000000
 R: 4:1 00 00 00 00 00 00 000000
 S: 4:2 00 80 00 00 00 00 000000
 T: 4:3 00 01 00 00 00 00 000000
 U: 5:0 00 00 00 00 00 00 000000
 V: 5:1 02 00 00 02 00 00 000000
 W: 5:2 00 00 00 00 00 00 000000
 X: 5:3 78 08 08 70 00 60 606000
 Y: 6:0 02 00 00 02 00 00 000000
 Z: 6:1 0e 08 00 04 00 04 000400
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 00 00 00 00 00 00 000000
CC: 7:0 92 80 80 00 00 12 121200
DD: 7:1 00 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000

But this doesn’t change the SPI result. The SPI still does not work on the production eMMC module, and works perfectly fine with the devkit modules. Already I’ve applied kernel patches, dtb patches and reflashed the modules just to enable something as simple as SPI. Is there a real working solution here that I can use or should I escalate this somehow? My time to solve this problem isn’t unlimited.

Apply this patch without the kernel GPIO patch and add the 40pin head SPI pin configure.

diff --git a/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-a02.dtsi b/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-a02.dtsi
index b520de5..56f9140 100644
--- a/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-a02.dtsi
+++ b/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-a02.dtsi
@@ -1,6 +1,6 @@
-/*This dtsi file was generated by T210_P3448_SKU2_pinmux.xlsm Revision: 8 */
+/*This dtsi file was generated by jetson_nano_module.xlsm Revision: 1.05 */
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,35 +26,13 @@
 
 		gpio_default: default {
 			gpio-input = <
-				TEGRA_GPIO(BB, 0)
-				TEGRA_GPIO(B, 4)
-				TEGRA_GPIO(B, 5)
-				TEGRA_GPIO(B, 6)
-				TEGRA_GPIO(B, 7)
-				TEGRA_GPIO(DD, 0)
-				TEGRA_GPIO(E, 6)
-				TEGRA_GPIO(S, 5)
 				TEGRA_GPIO(A, 5)
 				TEGRA_GPIO(X, 4)
 				TEGRA_GPIO(X, 5)
 				TEGRA_GPIO(X, 6)
 				TEGRA_GPIO(Y, 1)
-				TEGRA_GPIO(Y, 2)
-				TEGRA_GPIO(V, 0)
 				TEGRA_GPIO(V, 1)
-				TEGRA_GPIO(Z, 0)
 				TEGRA_GPIO(Z, 2)
-				TEGRA_GPIO(J, 5)
-				TEGRA_GPIO(J, 6)
-				TEGRA_GPIO(J, 4)
-				TEGRA_GPIO(J, 7)
-				TEGRA_GPIO(G, 2)
-				TEGRA_GPIO(G, 3)
-				TEGRA_GPIO(C, 0)
-				TEGRA_GPIO(C, 1)
-				TEGRA_GPIO(C, 2)
-				TEGRA_GPIO(C, 3)
-				TEGRA_GPIO(C, 4)
 				TEGRA_GPIO(H, 2)
 				TEGRA_GPIO(H, 5)
 				TEGRA_GPIO(H, 6)
@@ -64,7 +42,6 @@
 			gpio-output-low = <
 				TEGRA_GPIO(S, 7)
 				TEGRA_GPIO(T, 0)
-				TEGRA_GPIO(A, 6)
 				TEGRA_GPIO(Z, 3)
 				TEGRA_GPIO(H, 0)
 				TEGRA_GPIO(H, 3)
@@ -74,7 +51,9 @@
 				TEGRA_GPIO(I, 2)
 				>;
 			gpio-output-high = <
+				TEGRA_GPIO(A, 6)
 				TEGRA_GPIO(X, 3)
+				TEGRA_GPIO(CC, 7)
 				>;
 		};
 	};
diff --git a/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi b/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi
index ac8bda8..56f9140 100644
--- a/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi
+++ b/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi
@@ -1,6 +1,6 @@
-/*This dtsi file was generated by T210_P3448_SKU2_pinmux.xlsm Revision: 17 */
+/*This dtsi file was generated by jetson_nano_module.xlsm Revision: 1.05 */
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,43 +26,23 @@
 
 		gpio_default: default {
 			gpio-input = <
-				TEGRA_GPIO(BB, 0)
-				TEGRA_GPIO(B, 4)
-				TEGRA_GPIO(B, 5)
-				TEGRA_GPIO(B, 6)
-				TEGRA_GPIO(B, 7)
-				TEGRA_GPIO(DD, 0)
-				TEGRA_GPIO(E, 6)
-				TEGRA_GPIO(S, 5)
 				TEGRA_GPIO(A, 5)
 				TEGRA_GPIO(X, 4)
 				TEGRA_GPIO(X, 5)
 				TEGRA_GPIO(X, 6)
 				TEGRA_GPIO(Y, 1)
-				TEGRA_GPIO(Y, 2)
-				TEGRA_GPIO(V, 0)
 				TEGRA_GPIO(V, 1)
-				TEGRA_GPIO(Z, 0)
 				TEGRA_GPIO(Z, 2)
-				TEGRA_GPIO(J, 5)
-				TEGRA_GPIO(J, 6)
-				TEGRA_GPIO(J, 4)
-				TEGRA_GPIO(J, 7)
-				TEGRA_GPIO(G, 2)
-				TEGRA_GPIO(G, 3)
-				TEGRA_GPIO(C, 0)
-				TEGRA_GPIO(C, 1)
-				TEGRA_GPIO(C, 2)
-				TEGRA_GPIO(C, 3)
-				TEGRA_GPIO(C, 4)
 				TEGRA_GPIO(H, 2)
 				TEGRA_GPIO(H, 5)
 				TEGRA_GPIO(H, 6)
+				TEGRA_GPIO(I, 1)
 				TEGRA_GPIO(CC, 4)
 				>;
 			gpio-output-low = <
 				TEGRA_GPIO(S, 7)
 				TEGRA_GPIO(T, 0)
+				TEGRA_GPIO(Z, 3)
 				TEGRA_GPIO(H, 0)
 				TEGRA_GPIO(H, 3)
 				TEGRA_GPIO(H, 4)
@@ -73,7 +53,6 @@
 			gpio-output-high = <
 				TEGRA_GPIO(A, 6)
 				TEGRA_GPIO(X, 3)
-				TEGRA_GPIO(I, 1)
 				TEGRA_GPIO(CC, 7)
 				>;
 		};
diff --git a/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0002-a02.dtsi b/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0002-a02.dtsi
index 5d889ec..9be96f8 100644
--- a/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0002-a02.dtsi
+++ b/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0002-a02.dtsi
@@ -1,6 +1,6 @@
-/*This dtsi file was generated by T210_P3448_SKU2_pinmux.xlsm Revision: 8 */
+/*This dtsi file was generated by jetson_nano_module.xlsm Revision: 1.05 */
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -135,7 +135,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
 			};
 
 			pex_l0_rst_n_pa0 {
@@ -144,7 +144,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
 			};
 
 			pex_l1_clkreq_n_pa4 {
@@ -153,7 +153,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
 			};
 
 			pex_l1_rst_n_pa3 {
@@ -162,7 +162,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
 			};
 
 			pex_wake_n_pa2 {
@@ -171,7 +171,55 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc1_clk_pm0 {
+				nvidia,pins = "sdmmc1_clk_pm0";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc1_cmd_pm1 {
+				nvidia,pins = "sdmmc1_cmd_pm1";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc1_dat0_pm5 {
+				nvidia,pins = "sdmmc1_dat0_pm5";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc1_dat1_pm4 {
+				nvidia,pins = "sdmmc1_dat1_pm4";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc1_dat2_pm3 {
+				nvidia,pins = "sdmmc1_dat2_pm3";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc1_dat3_pm2 {
+				nvidia,pins = "sdmmc1_dat3_pm2";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 			};
 
 			sdmmc3_clk_pp0 {
@@ -264,6 +312,14 @@
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 			};
 
+			clk_32k_out_py5 {
+				nvidia,pins = "clk_32k_out_py5";
+				nvidia,function = "soc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
 			pz1 {
 				nvidia,pins = "pz1";
 				nvidia,function = "sdmmc1";
@@ -495,70 +551,6 @@
 			};
 
 			/* GPIO Pin Configuration */
-			aud_mclk_pbb0 {
-				nvidia,pins = "aud_mclk_pbb0";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi2_mosi_pb4 {
-				nvidia,pins = "spi2_mosi_pb4";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi2_miso_pb5 {
-				nvidia,pins = "spi2_miso_pb5";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi2_sck_pb6 {
-				nvidia,pins = "spi2_sck_pb6";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi2_cs0_pb7 {
-				nvidia,pins = "spi2_cs0_pb7";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi2_cs1_pdd0 {
-				nvidia,pins = "spi2_cs1_pdd0";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			pe6 {
-				nvidia,pins = "pe6";
-				nvidia,function = "rsvd0";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			cam_af_en_ps5 {
-				nvidia,pins = "cam_af_en_ps5";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
 			cam1_pwdn_ps7 {
 				nvidia,pins = "cam1_pwdn_ps7";
 				nvidia,function = "rsvd1";
@@ -631,22 +623,6 @@
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 			};
 
-			lcd_te_py2 {
-				nvidia,pins = "lcd_te_py2";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			lcd_bl_pwm_pv0 {
-				nvidia,pins = "lcd_bl_pwm_pv0";
-				nvidia,function = "rsvd3";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
 			lcd_bl_en_pv1 {
 				nvidia,pins = "lcd_bl_en_pv1";
 				nvidia,function = "rsvd0";
@@ -655,14 +631,6 @@
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 			};
 
-			pz0 {
-				nvidia,pins = "pz0";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
 			pz2 {
 				nvidia,pins = "pz2";
 				nvidia,function = "rsvd2";
@@ -679,94 +647,6 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			dap4_din_pj5 {
-				nvidia,pins = "dap4_din_pj5";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			dap4_dout_pj6 {
-				nvidia,pins = "dap4_dout_pj6";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			dap4_fs_pj4 {
-				nvidia,pins = "dap4_fs_pj4";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			dap4_sclk_pj7 {
-				nvidia,pins = "dap4_sclk_pj7";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			uart2_rts_pg2 {
-				nvidia,pins = "uart2_rts_pg2";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			uart2_cts_pg3 {
-				nvidia,pins = "uart2_cts_pg3";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi1_mosi_pc0 {
-				nvidia,pins = "spi1_mosi_pc0";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi1_miso_pc1 {
-				nvidia,pins = "spi1_miso_pc1";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi1_sck_pc2 {
-				nvidia,pins = "spi1_sck_pc2";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi1_cs0_pc3 {
-				nvidia,pins = "spi1_cs0_pc3";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi1_cs1_pc4 {
-				nvidia,pins = "spi1_cs1_pc4";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
 			wifi_en_ph0 {
 				nvidia,pins = "wifi_en_ph0";
 				nvidia,function = "rsvd0";
@@ -834,8 +714,8 @@
 			nfc_int_pi1 {
 				nvidia,pins = "nfc_int_pi1";
 				nvidia,function = "rsvd0";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 			};
 
@@ -847,6 +727,15 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
+			pcc7 {
+				nvidia,pins = "pcc7";
+				nvidia,function = "rsvd0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+			};
+
 			usb_vbus_en0_pcc4 {
 				nvidia,pins = "usb_vbus_en0_pcc4";
 				nvidia,function = "rsvd1";
@@ -858,6 +747,14 @@
 		};
 
 		pinmux_unused_lowpower: unused_lowpower {
+			aud_mclk_pbb0 {
+				nvidia,pins = "aud_mclk_pbb0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
 			dvfs_clk_pbb2 {
 				nvidia,pins = "dvfs_clk_pbb2";
 				nvidia,function = "rsvd0";
@@ -914,89 +811,97 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			dmic3_clk_pe4 {
-				nvidia,pins = "dmic3_clk_pe4";
+			spi2_mosi_pb4 {
+				nvidia,pins = "spi2_mosi_pb4";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			dmic3_dat_pe5 {
-				nvidia,pins = "dmic3_dat_pe5";
+			spi2_miso_pb5 {
+				nvidia,pins = "spi2_miso_pb5";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			cam_rst_ps4 {
-				nvidia,pins = "cam_rst_ps4";
-				nvidia,function = "rsvd1";
+			spi2_sck_pb6 {
+				nvidia,pins = "spi2_sck_pb6";
+				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			cam_flash_en_ps6 {
-				nvidia,pins = "cam_flash_en_ps6";
+			spi2_cs0_pb7 {
+				nvidia,pins = "spi2_cs0_pb7";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			cam1_strobe_pt1 {
-				nvidia,pins = "cam1_strobe_pt1";
+			spi2_cs1_pdd0 {
+				nvidia,pins = "spi2_cs1_pdd0";
 				nvidia,function = "rsvd1";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_clk_pm0 {
-				nvidia,pins = "sdmmc1_clk_pm0";
-				nvidia,function = "rsvd1";
+			dmic3_clk_pe4 {
+				nvidia,pins = "dmic3_clk_pe4";
+				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_cmd_pm1 {
-				nvidia,pins = "sdmmc1_cmd_pm1";
+			dmic3_dat_pe5 {
+				nvidia,pins = "dmic3_dat_pe5";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_dat0_pm5 {
-				nvidia,pins = "sdmmc1_dat0_pm5";
+			pe6 {
+				nvidia,pins = "pe6";
+				nvidia,function = "rsvd0";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			cam_rst_ps4 {
+				nvidia,pins = "cam_rst_ps4";
 				nvidia,function = "rsvd1";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_dat1_pm4 {
-				nvidia,pins = "sdmmc1_dat1_pm4";
+			cam_af_en_ps5 {
+				nvidia,pins = "cam_af_en_ps5";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_dat2_pm3 {
-				nvidia,pins = "sdmmc1_dat2_pm3";
+			cam_flash_en_ps6 {
+				nvidia,pins = "cam_flash_en_ps6";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_dat3_pm2 {
-				nvidia,pins = "sdmmc1_dat3_pm2";
-				nvidia,function = "rsvd2";
+			cam1_strobe_pt1 {
+				nvidia,pins = "cam1_strobe_pt1";
+				nvidia,function = "rsvd1";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1058,6 +963,22 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
+			lcd_te_py2 {
+				nvidia,pins = "lcd_te_py2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_bl_pwm_pv0 {
+				nvidia,pins = "lcd_bl_pwm_pv0";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
 			lcd_rst_pv2 {
 				nvidia,pins = "lcd_rst_pv2";
 				nvidia,function = "rsvd0";
@@ -1082,9 +1003,9 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			clk_32k_out_py5 {
-				nvidia,pins = "clk_32k_out_py5";
-				nvidia,function = "rsvd2";
+			pz0 {
+				nvidia,pins = "pz0";
+				nvidia,function = "rsvd1";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1114,6 +1035,54 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
+			dap4_din_pj5 {
+				nvidia,pins = "dap4_din_pj5";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			dap4_dout_pj6 {
+				nvidia,pins = "dap4_dout_pj6";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			dap4_fs_pj4 {
+				nvidia,pins = "dap4_fs_pj4";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			dap4_sclk_pj7 {
+				nvidia,pins = "dap4_sclk_pj7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_rts_pg2 {
+				nvidia,pins = "uart2_rts_pg2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_cts_pg3 {
+				nvidia,pins = "uart2_cts_pg3";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
 			uart1_rts_pu2 {
 				nvidia,pins = "uart1_rts_pu2";
 				nvidia,function = "rsvd1";
@@ -1210,6 +1179,46 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
+			spi1_mosi_pc0 {
+				nvidia,pins = "spi1_mosi_pc0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_miso_pc1 {
+				nvidia,pins = "spi1_miso_pc1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_sck_pc2 {
+				nvidia,pins = "spi1_sck_pc2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_cs0_pc3 {
+				nvidia,pins = "spi1_cs0_pc3";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_cs1_pc4 {
+				nvidia,pins = "spi1_cs1_pc4";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
 			spi4_mosi_pc7 {
 				nvidia,pins = "spi4_mosi_pc7";
 				nvidia,function = "rsvd1";
@@ -1306,15 +1315,6 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			pcc7 {
-				nvidia,pins = "pcc7";
-				nvidia,function = "rsvd0";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
-				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
-			};
-
 			spdif_out_pcc2 {
 				nvidia,pins = "spdif_out_pcc2";
 				nvidia,function = "rsvd1";
diff --git a/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0002-b00.dtsi b/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0002-b00.dtsi
index 60e5bb4..9be96f8 100644
--- a/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0002-b00.dtsi
+++ b/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0002-b00.dtsi
@@ -1,6 +1,6 @@
-/*This dtsi file was generated by T210_P3448_SKU2_pinmux.xlsm Revision: 17 */
+/*This dtsi file was generated by jetson_nano_module.xlsm Revision: 1.05 */
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -174,6 +174,54 @@
 				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
 			};
 
+			sdmmc1_clk_pm0 {
+				nvidia,pins = "sdmmc1_clk_pm0";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc1_cmd_pm1 {
+				nvidia,pins = "sdmmc1_cmd_pm1";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc1_dat0_pm5 {
+				nvidia,pins = "sdmmc1_dat0_pm5";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc1_dat1_pm4 {
+				nvidia,pins = "sdmmc1_dat1_pm4";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc1_dat2_pm3 {
+				nvidia,pins = "sdmmc1_dat2_pm3";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc1_dat3_pm2 {
+				nvidia,pins = "sdmmc1_dat3_pm2";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
 			sdmmc3_clk_pp0 {
 				nvidia,pins = "sdmmc3_clk_pp0";
 				nvidia,function = "sdmmc3";
@@ -272,6 +320,14 @@
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 			};
 
+			pz1 {
+				nvidia,pins = "pz1";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
 			pz5 {
 				nvidia,pins = "pz5";
 				nvidia,function = "soc";
@@ -495,70 +551,6 @@
 			};
 
 			/* GPIO Pin Configuration */
-			aud_mclk_pbb0 {
-				nvidia,pins = "aud_mclk_pbb0";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi2_mosi_pb4 {
-				nvidia,pins = "spi2_mosi_pb4";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi2_miso_pb5 {
-				nvidia,pins = "spi2_miso_pb5";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi2_sck_pb6 {
-				nvidia,pins = "spi2_sck_pb6";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi2_cs0_pb7 {
-				nvidia,pins = "spi2_cs0_pb7";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi2_cs1_pdd0 {
-				nvidia,pins = "spi2_cs1_pdd0";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			pe6 {
-				nvidia,pins = "pe6";
-				nvidia,function = "rsvd0";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			cam_af_en_ps5 {
-				nvidia,pins = "cam_af_en_ps5";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
 			cam1_pwdn_ps7 {
 				nvidia,pins = "cam1_pwdn_ps7";
 				nvidia,function = "rsvd1";
@@ -631,22 +623,6 @@
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 			};
 
-			lcd_te_py2 {
-				nvidia,pins = "lcd_te_py2";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			lcd_bl_pwm_pv0 {
-				nvidia,pins = "lcd_bl_pwm_pv0";
-				nvidia,function = "rsvd3";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
 			lcd_bl_en_pv1 {
 				nvidia,pins = "lcd_bl_en_pv1";
 				nvidia,function = "rsvd0";
@@ -655,14 +631,6 @@
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 			};
 
-			pz0 {
-				nvidia,pins = "pz0";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
 			pz2 {
 				nvidia,pins = "pz2";
 				nvidia,function = "rsvd2";
@@ -671,92 +639,12 @@
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 			};
 
-			dap4_din_pj5 {
-				nvidia,pins = "dap4_din_pj5";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			dap4_dout_pj6 {
-				nvidia,pins = "dap4_dout_pj6";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			dap4_fs_pj4 {
-				nvidia,pins = "dap4_fs_pj4";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			dap4_sclk_pj7 {
-				nvidia,pins = "dap4_sclk_pj7";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			uart2_rts_pg2 {
-				nvidia,pins = "uart2_rts_pg2";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			uart2_cts_pg3 {
-				nvidia,pins = "uart2_cts_pg3";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi1_mosi_pc0 {
-				nvidia,pins = "spi1_mosi_pc0";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi1_miso_pc1 {
-				nvidia,pins = "spi1_miso_pc1";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi1_sck_pc2 {
-				nvidia,pins = "spi1_sck_pc2";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi1_cs0_pc3 {
-				nvidia,pins = "spi1_cs0_pc3";
-				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-			};
-
-			spi1_cs1_pc4 {
-				nvidia,pins = "spi1_cs1_pc4";
+			pz3 {
+				nvidia,pins = "pz3";
 				nvidia,function = "rsvd1";
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
 			wifi_en_ph0 {
@@ -827,8 +715,8 @@
 				nvidia,pins = "nfc_int_pi1";
 				nvidia,function = "rsvd0";
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
-				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 			};
 
 			gps_en_pi2 {
@@ -859,6 +747,14 @@
 		};
 
 		pinmux_unused_lowpower: unused_lowpower {
+			aud_mclk_pbb0 {
+				nvidia,pins = "aud_mclk_pbb0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
 			dvfs_clk_pbb2 {
 				nvidia,pins = "dvfs_clk_pbb2";
 				nvidia,function = "rsvd0";
@@ -915,89 +811,97 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			dmic3_clk_pe4 {
-				nvidia,pins = "dmic3_clk_pe4";
+			spi2_mosi_pb4 {
+				nvidia,pins = "spi2_mosi_pb4";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			dmic3_dat_pe5 {
-				nvidia,pins = "dmic3_dat_pe5";
+			spi2_miso_pb5 {
+				nvidia,pins = "spi2_miso_pb5";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			cam_rst_ps4 {
-				nvidia,pins = "cam_rst_ps4";
-				nvidia,function = "rsvd1";
+			spi2_sck_pb6 {
+				nvidia,pins = "spi2_sck_pb6";
+				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			cam_flash_en_ps6 {
-				nvidia,pins = "cam_flash_en_ps6";
+			spi2_cs0_pb7 {
+				nvidia,pins = "spi2_cs0_pb7";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			cam1_strobe_pt1 {
-				nvidia,pins = "cam1_strobe_pt1";
+			spi2_cs1_pdd0 {
+				nvidia,pins = "spi2_cs1_pdd0";
 				nvidia,function = "rsvd1";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_clk_pm0 {
-				nvidia,pins = "sdmmc1_clk_pm0";
-				nvidia,function = "rsvd1";
+			dmic3_clk_pe4 {
+				nvidia,pins = "dmic3_clk_pe4";
+				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_cmd_pm1 {
-				nvidia,pins = "sdmmc1_cmd_pm1";
+			dmic3_dat_pe5 {
+				nvidia,pins = "dmic3_dat_pe5";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_dat0_pm5 {
-				nvidia,pins = "sdmmc1_dat0_pm5";
+			pe6 {
+				nvidia,pins = "pe6";
+				nvidia,function = "rsvd0";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			cam_rst_ps4 {
+				nvidia,pins = "cam_rst_ps4";
 				nvidia,function = "rsvd1";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_dat1_pm4 {
-				nvidia,pins = "sdmmc1_dat1_pm4";
+			cam_af_en_ps5 {
+				nvidia,pins = "cam_af_en_ps5";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_dat2_pm3 {
-				nvidia,pins = "sdmmc1_dat2_pm3";
+			cam_flash_en_ps6 {
+				nvidia,pins = "cam_flash_en_ps6";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			sdmmc1_dat3_pm2 {
-				nvidia,pins = "sdmmc1_dat3_pm2";
-				nvidia,function = "rsvd2";
+			cam1_strobe_pt1 {
+				nvidia,pins = "cam1_strobe_pt1";
+				nvidia,function = "rsvd1";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1059,6 +963,22 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
+			lcd_te_py2 {
+				nvidia,pins = "lcd_te_py2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_bl_pwm_pv0 {
+				nvidia,pins = "lcd_bl_pwm_pv0";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
 			lcd_rst_pv2 {
 				nvidia,pins = "lcd_rst_pv2";
 				nvidia,function = "rsvd0";
@@ -1083,16 +1003,8 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
-			pz1 {
-				nvidia,pins = "pz1";
-				nvidia,function = "rsvd2";
-				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
-				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-			};
-
-			pz3 {
-				nvidia,pins = "pz3";
+			pz0 {
+				nvidia,pins = "pz0";
 				nvidia,function = "rsvd1";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
@@ -1123,6 +1035,54 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
+			dap4_din_pj5 {
+				nvidia,pins = "dap4_din_pj5";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			dap4_dout_pj6 {
+				nvidia,pins = "dap4_dout_pj6";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			dap4_fs_pj4 {
+				nvidia,pins = "dap4_fs_pj4";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			dap4_sclk_pj7 {
+				nvidia,pins = "dap4_sclk_pj7";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_rts_pg2 {
+				nvidia,pins = "uart2_rts_pg2";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_cts_pg3 {
+				nvidia,pins = "uart2_cts_pg3";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
 			uart1_rts_pu2 {
 				nvidia,pins = "uart1_rts_pu2";
 				nvidia,function = "rsvd1";
@@ -1219,6 +1179,46 @@
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 			};
 
+			spi1_mosi_pc0 {
+				nvidia,pins = "spi1_mosi_pc0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_miso_pc1 {
+				nvidia,pins = "spi1_miso_pc1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_sck_pc2 {
+				nvidia,pins = "spi1_sck_pc2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_cs0_pc3 {
+				nvidia,pins = "spi1_cs0_pc3";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_cs1_pc4 {
+				nvidia,pins = "spi1_cs1_pc4";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
 			spi4_mosi_pc7 {
 				nvidia,pins = "spi4_mosi_pc7";
 				nvidia,function = "rsvd1";
-- 

I reverted the changes, and applied the patch. It didn’t work. However, dmsg reveals that 700008d4.spi seems to have been added.

I added ONLY the header-40pin-pinmux to the dtb, it did not work. (also, the header-40pin-pinmux node ended up in common instead of with the pinmux@700008d4)

I changed part of the pinmux@700008d4 to have the pinctrl-0 values match the phandle. Now it doesn’t even boot. log.txt (33.5 KB)

I really don’t have time to patch, reflash, patch, flash, patch all day. Please provide a working kernel image with a working dtb file. Then we can figure out what the details are once I have a working example.

What’s the result from below command after for the device tree patch.
Also what REG to solve by devmem.

sudo cat /sys/kernel/debug/tegra_gpio

Since it didn’t seem like we were making any progress and going in circles, I dedicated my morning to digging deep into what was going on with the device tree.

It turns out that in addition to jetson-io not working with the production version of the nano (it seems like its missing the overlay .dtbo files that are needed) the dtsi files are also not included properly. I found this out when I tried to apply this patch 0001-configure-SPI-pins.patch.txt (2.6 KB) from this thread and found that the SPI pins were not allocated properly. I used dtc to decompile the device tree blob and found that the dtsi changes were not reflected. I manually changed the decompiled device tree and translated the labels for TEGRA_*, recompiled it into a blob and flashed the device. spidev_test now works as expected.

I very highly recommend that nvidia spends some time getting jetson-io to work with all the expected overlays and address the issue with the kernel build system.

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