jetpack 4.2.1 Supports FreeRTOS for SPE (Cortex-R5) BUT THERE IS NO TUTORIAL !

Hello, quincy4xh9j:
Please check doc/devicetree-ivc.md, and you can echo/cat /sys/devices/aon_cho/data_channel.
Refer to code for details.

br
Chenjian

Hello jachen,

static portTASK_FUNCTION(gpio_app_task, pvParameters)
{
	(void)pvParameters;
	int val;

	val = gpio_direction_out(GPIO_APP_OUT, 0);
	if (val) {
		error_hook("gpio_direction_out failed\r\n");
		return;
	}
	val = gpio_direction_in(GPIO_APP_IN);
	if (val) {
		error_hook("gpio_direction_in failed\r\n");
		return;
	}

	val = gpio_set_irq_type(GPIO_APP_IN, GPIO_IRQ_SINGLE_EDGE,
				GPIO_IRQ_RISING_EDGE);
	if (val) {
		error_hook("gpio_set_irq_type failed\r\n");
		return;
	}

	val = gpio_set_irq_handler(GPIO_APP_IN, can_gpio_irq_handler, NULL);
	if (val) {
		error_hook("gpio_set_irq_handler failed\r\n");
		return;
	}

	val = gpio_enable_irq(GPIO_APP_IN);
	if (val) {
		error_hook("gpio_enable_irq failed\r\n");
		return;
	}

	while (1) {
		printf("%s - Setting GPIO_APP_OUT to 1 - IRQ should trigger\r\n",
		       __func__);
		gpio_set_value(GPIO_APP_OUT, 1);
		vTaskDelay(GPIO_OUT_SET_DELAY);
		gpio_set_value(GPIO_APP_OUT, 0);
		vTaskDelay(GPIO_OUT_SET_DELAY);
	};
}

void gpio_app_init(void)
{
	int val = xTaskCreate(gpio_app_task, "gpioapp", 512, NULL,
			      tskIDLE_PRIORITY, NULL);
	if (val != pdPASS)
		error_hook("xTaskCreate for gpio_app_task failed\r\n");
}

I tried blink led with this app. I enabled , ENABLE_GPIO_APP := 1 this predefined. But I didn’t get inside following while loop. I had debugged with uart.

while (1) {
		printf("%s - Setting GPIO_APP_OUT to 1 - IRQ should trigger\r\n",
		       __func__);
		gpio_set_value(GPIO_APP_OUT, 1);
		vTaskDelay(GPIO_OUT_SET_DELAY);
		gpio_set_value(GPIO_APP_OUT, 0);
		vTaskDelay(GPIO_OUT_SET_DELAY);
	};

Why this loop is not running ? I put a led to pins 17 of J26.

Hi jachen,

Please tell me where is the “SPE firmware source code” code?

Hello, hamzaygrtc:
With UART connected, have you ever seen logs like:

main enter
SPE VERSION #: ... ...
HW Function test
Start Scheduler.
in late init

If not, please check your platform and maybe something’s wrong.
If yes, you can add some debug information step by step and make sure the FW runs as you desired.

br
Chenjian

Hello, garretzou:
https://developer.nvidia.com/embedded/downloads#?search=SPE

br
Chenjian

Hello jachen,

Im using tegra_uart_write_now function for send a message through uart. If I write message somewhere I could take it on my host pc. But I couldn’t take over pins. How could I change {value,out,in…} of j21,j26 pins.

char tx_message[] = "Message from SPE R5 UART\r\n";
	int tx_len = sizeof(tx_message) - 1;

	(void)pvParameters;

	for (;;) {
		tegra_uart_write_now(&UART_APP_PORT, tx_message, tx_len);
		vTaskDelay(UART_SET_DELAY);
	};

Hello, hamzaygrtc:
The code clip you pasted is for UART test. In TX2, SPE FW will output that message to UARTC.
But for SPE FW debug, the message like print/print_isr will be output to UARTG.

So you have to fly wire from UARTG and check the print message from SPE FW.

br
Chenjian

I had flied wire to UARTG output is

There are lot of booting things...
...
...
...
<hit enter to active fiq debugger>

I entered but does not happened anything.

Hello, hamzaygrtc:
It seems that the log you pasted does not come from UARTG. It’s the main debug port which shows Linux boot log of CCPLEX. The default SPE FW log in TX2 r32.2 should look like: (It will mess with some other messages, just ignore unrelated logs.)

main enter
SPE VERSION #: ... ...
HW Function test
Start Scheduler.
in late init

Please setup the device correctly and then you can do further SPE FW development/debug.

br
ChenJian

Hi jachen,

I couldn’t get like this output. I connect my ttl cable to j17 pins 5 and 4. then looking with ‘putty’.
Just output:

Message from SPE R5 UART

Hello, hamzaygrtc:
The UART port you attached is the tested UART port (UARTC in TX2 TRM, UART1_TXD/RXD in TX2 carrier board schematic.) You can see that message means SPE FW runs correctly.

SPE FW debug information will be output to another UART port (UARTG in TX2 TRM, UART4_TX/RX in TX2 carrier board schematic.)

br
Chenjian

I checked carrier board schematic. my board:
[url]https://icdn7.digitaltrends.com/image/digitaltrends/jetsontx2-03-640x640.jpg[/url]

How could I connect with ttl cable ? There are no pins for uart4

Hello, hamzaygrtc:
Please take a look at FreeRTOS SPE-fw help for pin control - Jetson TX2 - NVIDIA Developer Forums
there’s some detailed description for UART and GPIO.

br
Chenjian

Hi jachen,

I did GPIO app ,thanks for that. :)

I checked Jetson Download Center | NVIDIA Developer -P2597_C02_Concept_schematics.pdf- UARTG is

on j10 ? If j10 has uartg/rt-rx, I’ll fly wires from resistors to access or what kind of connector I can

use for j10 ?

hi jachen could you help for this?

Hello, hamzaygrtc;
Yes, UARTG rx/tx pins are connected to J10. Flying wires from corresponding resistors is an easy way. Or you have to make your own circuit with daughter connector to export those pins, which may be harder.

br
Chenjian