I recently worked on upgrading JetPack from 3.3 to 4.6
There’s a problem with the camera。
I get an error when I use v4l2-ctl to plot video0
v4l2-ctl -d /dev/video0 --set-fmt-video=width=2560,height=720,pixelformat=RG12 --stream-mmap --stream-count=1
[87842.806788] ov490 2-004d: camera_common_mclk_disable: disable MCLK
[87848.551304] ov490 2-004d: camera_common_mclk_enable: enable MCLK with 24000000 Hz
[87848.551336] ov490 2-004d: camera_common_dpd_disable: csi 0
[87848.551359] ov490 2-004d: camera_common_dpd_disable: csi 1
[87848.551362] ov490_power_on, unimplement function...
[87848.552570] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[87848.552573] nvcsi 150c0000.nvcsi: csi_port: 0
[87848.552723] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[87848.552726] nvcsi 150c0000.nvcsi: csi_port: 2
[87848.553230] ov490 2-004d: camera_common_try_fmt: size 2560 x 720
[87848.553239] ov490 2-004d: camera_common_s_fmt(12306) size 2560 x 720
[87848.553243] ov490 2-004d: camera_common_try_fmt: size 2560 x 720
[87848.559357] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=4
[87848.559362] nvcsi 150c0000.nvcsi: csi4_stream_init
[87848.559376] nvcsi 150c0000.nvcsi: csi4_stream_config
[87848.559384] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[87848.559387] nvcsi 150c0000.nvcsi: settle time reading from of_node
[87848.559391] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[87848.559393] nvcsi 150c0000.nvcsi: discontinuous_clk = 1 from of_node
[87848.559396] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[87848.559398] nvcsi 150c0000.nvcsi: csi4_phy_config
[87848.559403] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[87848.559412] nvcsi 150c0000.nvcsi: sig_props->serdes_pixel_clock.val: 0, sig_props->pixel_clock.val: 0
[87848.559415] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 0
[87848.559418] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[87848.559421] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 17
[87848.559435] ov490_set_mode, unimplement function...
[87848.559437] ov490_start_streaming, unimplement function...
[87848.763070] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[87848.769433] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[87848.779110] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=4
[87848.779114] nvcsi 150c0000.nvcsi: settle time reading from of_node
[87848.779118] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[87848.779121] nvcsi 150c0000.nvcsi: discontinuous_clk = 1 from of_node
[87848.779123] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[87848.779126] nvcsi 150c0000.nvcsi: csi4_phy_config
[87848.779132] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000004
[87848.779140] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[87848.779152] nvcsi 150c0000.nvcsi: csi4_cil_check_status 401
[87848.779158] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=4
[87848.779160] nvcsi 150c0000.nvcsi: csi4_stream_init
[87848.779173] nvcsi 150c0000.nvcsi: csi4_stream_config
[87848.779181] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[87848.779183] nvcsi 150c0000.nvcsi: settle time reading from of_node
[87848.779186] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[87848.779188] nvcsi 150c0000.nvcsi: discontinuous_clk = 1 from of_node
[87848.779190] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[87848.779192] nvcsi 150c0000.nvcsi: csi4_phy_config
[87848.779197] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000004
[87848.779206] nvcsi 150c0000.nvcsi: sig_props->serdes_pixel_clock.val: 0, sig_props->pixel_clock.val: 0
[87848.779209] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 0
[87848.779211] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[87848.779214] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 17
[87848.983077] tegra-vi4 15700000.vi: **PXL_SOF syncpt timeout! err = -11**
But video1 worker well
There is no problem with the hardware, both video0 and video1 worked with JetPAck3.3 on the slave side
Do you have any debug techniques？
Below is our hardware design diagram
device tree
#include "dt-bindings/clock/tegra186-clock.h"
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/gpio/tegra186-gpio.h>
/* camera control gpio definitions */
#define CAM0_RST_L TEGRA_MAIN_GPIO(R, 5)
#define CAM0_PWDN TEGRA_MAIN_GPIO(R, 0)
#define FLASH_EN TEGRA_MAIN_GPIO(X, 6)
#define FLASH_STROBE TEGRA_MAIN_GPIO(V, 5)
#define CAM1_RST_L TEGRA_MAIN_GPIO(R, 1)
#define CAM1_PWDN TEGRA_MAIN_GPIO(L, 6)
// #define CAM2_RST_L TEGRA_MAIN_GPIO(R, 1)
// #define CAM2_PWDN TEGRA_MAIN_GPIO(R, 0)
/ {
/* set camera gpio direction to output */
gpio@2200000 {
camera-control-output-low {
gpio-hog;
output-high;
gpios = <CAM0_RST_L 0 CAM0_PWDN 0>;
label = "cam0-rst", "cam0-pwdn";
};
};
host1x {
vi_base: vi@15700000 {
num-channels = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
vi_port0: port@0 {
reg = <0>;
status = "okay";
ov490_3d_vi_in0: endpoint {
port-index = <0>;
bus-width = <4>;
remote-endpoint = <&ov490_3d_csi_out0>;
status = "okay";
};
};
vi_port1: port@1 {
reg = <1>;
status = "okay";
ov490_30_vi_in0: endpoint {
port-index = <2>;
bus-width = <4>;
remote-endpoint = <&ov490_30_csi_out0>;
status = "okay";
};
};
};
};
csi_base: nvcsi@150c0000 {
num-channels = <2>;
#address-cells = <1>;
#size-cells = <0>;
csi_chan0: channel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
reg = <0>;
ov490_3d_csi_in0: endpoint@0 {
port-index = <0>;
bus-width = <4>;
status = "okay";
remote-endpoint = <&ov490_3d_out>;
};
};
port@1 {
reg = <1>;
ov490_3d_csi_out0: endpoint@1 {
status = "okay";
remote-endpoint = <&ov490_3d_vi_in0>;
};
};
};
};
csi_chan1: channel@1 {
reg = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
reg = <0>;
ov490_30_csi_in0: endpoint@2 {
port-index = <2>;
bus-width = <4>;
status = "okay";
remote-endpoint = <&ov490_30_out>;
};
};
port@1 {
reg = <1>;
ov490_30_csi_out0: endpoint@3 {
status = "okay";
remote-endpoint = <&ov490_30_vi_in0>;
};
};
};
};
};
};
/* I2C3 I2C_CAM_CLK/DAT */
i2c@3180000 {
ov490_d@3d {
status = "okay";
devnode = "video0";
compatible = "nvidia,ov490";
//fake reg address
reg = <0x5c>;
//compatible = "nvidia,imx219";
//reg = <0x10>;
clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>;
clock-names = "extperiph1";
mclk = "extperiph1";
reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
mode0 { // IMX219_MODE_1920X1080
mclk_khz = "24000";
mclk_multiplier = "25";
pix_clk_hz = "200000000";
//pix_clk_hz = "170000000";
num_lanes = "4";
tegra_sinterface = "serial_e";
pixel_t = "yuv_yuyv16";
active_w = "1280";
active_h = "720";
line_length = "2560";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ov490_3d_out: endpoint {
port-index = <0>;
bus-width = <4>;
remote-endpoint = <&ov490_3d_csi_in0>;
};
};
};
};
ov490_0@30 {
status = "okay";
devnode = "video1";
compatible = "nvidia,ov490";
//fake reg address
reg = <0x5e>;
//compatible = "nvidia,imx219";
//reg = <0x10>;
clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>;
clock-names = "extperiph1";
mclk = "extperiph1";
reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
mode0 { // IMX219_MODE_1920X1080
mclk_khz = "24000";
mclk_multiplier = "25";
pix_clk_hz = "200000000";
//pix_clk_hz = "170000000";
num_lanes = "4";
tegra_sinterface = "serial_e";
pixel_t = "yuv_yuyv16";
active_w = "1280";
active_h = "720";
line_length = "2560";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ov490_30_out: endpoint {
port-index = <2>;
bus-width = <4>;
remote-endpoint = <&ov490_30_csi_in0>;
};
};
};
};
};
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
num_csi_lanes = <8>;
max_lane_speed = <1500000>;
max_pixel_rate = <7500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
modules {
module0 {
badge = "uisee_center_v0";
position = "center";
orientation = "1";
status = "okay";
drivernode0 {
pcl_id = "v4l2_sensor";
proc-device-tree = "/proc/device-tree/i2c@3180000/ov490_d@3d";
status = "okay";
};
};
module1 {
badge = "uisee_center_v1";
position = "center";
orientation = "1";
status = "okay";
drivernode0 {
pcl_id = "v4l2_sensor";
proc-device-tree = "/proc/device-tree/i2c@3180000/ov490_0@30";
status = "okay";
};
};
};
};
};