Jetpack 5.0.2 : vi_capture_status: capture status timed out

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
1

My hardware connection path is: AWR2243 → DS90UB953-Q1 → DS90UB960-Q1 → Orin

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AWR2243 uses 4 lanes, and it’s data output rate is 400 Mbps/lane.
The configuration of AWR2243 is:

awr2243@28 {
                            compatible = "ti,awr2243";
                            mclk = "extperiph1";
                            physical_w = "10.4";
                            physical_h = "10.4";
                            sensor_model = "awr2243";
                            use_decibel_gain = "false";
                            use_sensor_mode_id = "true";
                            physical-addr = <0x28>;
                            #address-cells = <0x1>;
                            #size-cells = <0x0>;
                            status = "disabled";
                            reg = <0x60>;
                            devnode = "video0";
                            serializer = <0x4c>;
                            deserializer = <0x4d>;
                            phandle = <0x2fc>;

                            mode0 {
                                mclk_khz = "200000";
                                num_lanes = <4>;
                                tegra_sinterface = "serial_a";
                                phy_mode = "DPHY";
                                discontinuous_clk = "yes";
                                dpcm_enable = "false";
                                cil_settletime = <1>;
                                readout_orientation = <0>;
                                vc_id = <0>;
                                dynamic_pixel_bit_depth = <8>;
                                csi_pixel_bit_depth = <8>;
                                mode_type = "bayer";
                                pixel_phase = "rggb";
                                active_w = "4096";
                                active_h = "512";
                                line_length = "4096";
                                inherent_gain = <1>;
                                mclk_multiplier = <2>;
                                pix_clk_hz = "200000000";
                                serdes_pix_clk_hz = "800000000";
                                gain_factor = "10";
                                min_gain_val = <0>;
                                max_gain_val = <52>;
                                step_gain_val = <2>;
                                default_gain = <0>;
                                min_hdr_ratio = <1>;
                                max_hdr_ratio = <1>;
                                framerate_factor = "1000000";
                                min_framerate = "1500000";
                                max_framerate = "30000000";
                                step_framerate = <1>;
                                default_framerate = "30000000";
                                exposure_factor = "1000000";
                                min_exp_time = "30";
                                max_exp_time = "660000";
                                step_exp_time = <1>;
                                default_exp_time = "33334";
                                embedded_metadata_height = <1>;
                            };

                            ports {
                                #address-cells = <0x1>;
                                #size-cells = <0x0>;
                                status = "disabled";
                                port@0 {
                                    reg = <0x0>;

                                    endpoint {
                                        vc-id = <0x0>;
                                        status = "disabled";
                                        port-index = <0x0>;
                                        bus-width = <0x4>;
                                        remote-endpoint = <0x40>;
                                        phandle = <0x2fd>;
                                    };
                                };
                            };
};

Actually all control of the AWR224 is done by the radar controller via SPI. Orin only needs to receive data.
I use “v4l2-ctl --set-fmt-video=width=4096,height=512,pixelformat=RGGB --stream-mmap --stream-count=1 -d /dev/video0 --stream-to=radar .raw --stream-poll” to receive data, the log is as follows:

[  204.791593] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: stream=0, vc=2, csi_port=0
[  204.791595] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: vi_port=0
[  204.791882] awr2243 20-0062: awr2243_s_stream: enable
[  207.282682] tegra194-vi5 13e40000.host1x:vi0@15c00000: vi_capture_status: capture status timed out
[  207.291951] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[  207.301112] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[  207.311892] (NULL device *): vi_capture_control_message: NULL VI channel received
[  207.319618] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0, vi_port=0
[  207.331273] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_start_streaming: csi_pt=0, st_id=0, vc_id=0, pg_mode=0x0
[  207.331275] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_set_config: stream_id=0, csi_port=0
[  207.331278] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_set_config: cil_settingtime is pulled from device
[  207.331280] (NULL device *): vi_capture_control_message: NULL VI channel received
[  207.339001] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: stream=0, vc=2, csi_port=0
[  207.339004] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 2
[  207.349790] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel

The content of the trace is as follows:

# tracer: nop
#
# entries-in-buffer/entries-written: 11/11   #P:8
#
#                                _-----=> irqs-off
#                               / _----=> need-resched
#                              | / _---=> hardirq/softirq
#                              || / _--=> preempt-depth
#                              ||| /     delay
#           TASK-PID     CPU#  ||||   TIMESTAMP  FUNCTION
#              | |         |   ||||      |         |
     kworker/4:2-144     [004] ....   204.786527: rtcpu_vinotify_event: tstamp:7222406823 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:231102632800 data:0x379d580010000000
     kworker/4:2-144     [004] ....   204.786530: rtcpu_vinotify_event: tstamp:7222406973 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:231102639296 data:0x0000000031000001
     kworker/4:2-144     [004] ....   204.786530: rtcpu_vinotify_event: tstamp:7222407126 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:231102695488 data:0x379d550010000000
     kworker/4:2-144     [004] ....   204.786530: rtcpu_vinotify_event: tstamp:7222407257 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:231102702048 data:0x0000000031000002
     kworker/4:2-144     [004] ....   204.842887: rtcpu_nvcsi_intr: tstamp:7222622095 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000088
     kworker/4:2-144     [004] ....   204.842888: rtcpu_nvcsi_intr: tstamp:7222622095 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000088
     kworker/4:2-144     [004] ....   204.842888: rtcpu_nvcsi_intr: tstamp:7222626125 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x01c00000
     kworker/4:2-144     [004] ....   204.842889: rtcpu_nvcsi_intr: tstamp:7222626125 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00c00000
     kworker/4:2-144     [004] ....   207.366408: rtcpu_nvcsi_intr: tstamp:7302860381 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000088
     kworker/4:2-144     [004] ....   207.366412: rtcpu_nvcsi_intr: tstamp:7302860381 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000088
     kworker/4:2-144     [004] ....   212.745563: rtcpu_string: tstamp:7470580683 id:0x04010000 str:"VM0 deactivating."

Is there something wrong with the configuration or do I need to do something extra?

How to configure the parameters of the CSI receiver in jetpack 5.0.2?

3

hello wq.zhou,

there shows PHY interrupts, the error code 0x88 it means LP sequence error has detected on data-lane.
normally, the correct LP sequence it should follow by LP11->LP01->LP00->LP11 sequence.
hence, it’s more like a hardware, or serdes chip configuration issue.

4

Hello JerryChang,

I send analogue data on the DS90UB960-Q1 and read the data on the Orin with the same error log. the radar data is not forwarded at this time.

How is the CSI of the Orin configured?

In the csi4_start_streaming function in csi4_fops.c, the call “csi4_start_streaming->csi4_phy_config->csi4_phy_write->writel” shows that the CSI is being configured.

Orin calls csi5_start_streaming in csi5_fops.c, but I don’t understand how to configure CSI. How does it configure the number of lanes and the clock? Does it configure each channel according to sensor parameters?

5

hello wq.zhou,

it’s device tree to configure all those hardware specific settings.

BTW,
there’re some bug fixes related to SerDes chip camera use-case,
could you please moving to JP-5.1.1 to include the fixes and test again.
thanks

6

Hello JerryChang,

Is it the Ｏrin’s own CSI related configuration in the device tree or the sensor’s related configuration?

7

hello wq.zhou,

device tree include all of them,
there’re sensor_signal_properties / sensor_image_properties / sensor_control_properties.

they’re hardware specific settings, i.e. clocks, GPIOs, regulators…etc
sensor specific settings, i.e. slave add., width/height, pixel format, pixel clock…etc.
camera platform specific settings, i.e. all the settings within the field of tegra-camera-platform{…}
and… V4L2 media controller specific settings. i.e. those VI/CSI/sensor port bindings.

you may see-also developer guide, Sensor Software Driver Programming.

8

Hello JerryChang,

In my solution, Orin does not need to configure the radar sensor, and another MCU configures it through SPI, so is the csi configuration of the sensor in the device tree used for Orin’s CSI?

9

hello wq.zhou,

is this way, you should only report the port bindings to have correct device topology, and please also review pixel clock (i.e. serdes_pix_clk_hz) that’s match to MIPI signaling.

again,
could you please moving to JP-5.1.1 to include the fixes and test again.

10

Hello JerryChang,

I use the BSP provided by D3Engineering(GitHub - D3Engineering/d3-jetson-bsp at d3/6.1.0), a partner of nVidia, and compile it with JetPack_5.1.1_Linux_JETSON_AGX_ORIN_TARGETS. Is this all right?

12

Hi wq.zhou,

How does it configure the number of lanes and the clock? Does it configure each channel according to sensor parameters?

I don’t know the specifics of your sensor, but if I were to change the settings for our AR0234, I would start by searching for CSI_LANES. Our preprocessor templates replace the CSI_LANES macros defined for each camera/deserializer/serializer. You’ll find its definition in hardware/d3/d3-6x-serdes-cam0-3.dtsi (and a few other places). For the AR0234 we set num_lanes = STR(CSI_LANES) in hardware/d3/templated-cameras/d3-cam-ar0234-modes.dtsi. You’ll find a similar pattern for VC_ID (virtual channel), and several other parameters.

To set the deserializer output clock, you’ll want to look in hardware/d3/templated-deserializers/d3-des-ub960-template.dtsi for the csi-tx-speed-mbps property.

For Argus input clocks, you’ll have to look in the sensor-specific configuration files. For the 234, they are in hardware/d3/templated-cameras/d3-cam-ar0234-template.dtsi and hardware/d3/templated-cameras/d3-cam-ar0234-modes.dtsi. You’ll have to rely on NVIDIA’s documentation for what they all do.

Unfortunately we don’t support JetPack 5.1.1 with our BSP yet, and it likely won’t work correctly if you try installing it.

13

I have downgraded the JetPack version from 5.1.1 to 5.0.2. I enabled the Pattern Generator on UB960, and the register configuration refers to chapter 7.5.12.4 of the datasheet. The data is still not read, and the error is also an LP sequence error. Which parameter do I need to adjust to fix this issue? How to determine the value of this parameter?

14

it’s device tree property , cil_settletime to configure THS settle time of the MIPI lane, the unit is in nanoseconds.

15

What is the relationship between cil_settletime and THS settle time?

85 ns + 6×ui < (cil_settletime+6) × (lp_clock_period) < 145 ns + 10×ui
Where:

  • lp_clock_period is 1/(204 MHz).
  • ui is the unit interval, equal to the duration of the HS state on the clock lane.

In the above relational expression, does the value of lp_clock_period need to be divided by 1000 when calculating? If the sensor is in continuous clock mode, how to determine the value of UI? If serializers and deserializers are used, and one deserializer is connected to multiple serializers, does the value of the UI change?

16

hello wq.zhou,

there’s sequence, LP11->LP01->LP00->LP11
when moving from LP to HS. the settle time determine how many cscil clock cycles to wait after LP00.

however, do you still seeing the same PHY interrupts, with the error code 0x88?

17

Hello JerryChang,

Yes, i still seeing the same PHY interrupts with the error code 0x88.

kworker/3:3-153 [003] … 105.206208: rtcpu_nvcsi_intr: tstamp:4098316239 class:GLOBAL type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000088

18

The document( Jetson_Orin_NX_DS-10712-001_v0.5.pdf ) mentions:
The VI block receives data from the CSI receiver and prepares it for presentation to system memory or the dedicated image signal processor execution resources.

My question:
Which configuration determines ‘the data received by VI is placed in system memory or ISP’?

19

it may be driver issue. as mentioned by partner in comment #12.

you may see-also Approaches for Validating and Testing the V4L2 Driver.
if you using V4L2 IOCTL directly it’ll bypass ISP.

20

Hello JerryChang,

Thank you for your reply!

What I am more concerned about now is how to get the correct UI value, so as to calculate the correct value of cil_settletime. Can you help me?

21

hello wq.zhou,

do you have oscilloscope? you may probe the MIPI signaling to examine the LP sequence to tune the settle time.

22

Hello JerryChang,

If we use an oscilloscope to measure the signal, how do we observe the value of the UI?