Jetpack-5.1.2 - Disabling CRC check does not work

khang.l4es · August 12, 2024, 8:51am

Hello Community,

I would like to continue my previous discussion about disabling the CRC check in order to verify the FPGA simulating the IMX219.

Below are the steps :

Step 1 : Replace the TRCPU firmware with the one shared here then flash the board :

khang@NUC8i7HVK $ fd rtcpu /home/khang/Workspace/Ref/Platforms/Nvidia/Jetson/sdk_install/JetPack_5.1.2_Linux_JETSON_XAVIER_NX_TARGETS/Linux_for_Tegra/
/home/khang/Workspace/Ref/Platforms/Nvidia/Jetson/sdk_install/JetPack_5.1.2_Linux_JETSON_XAVIER_NX_TARGETS/Linux_for_Tegra/bootloader/camera-rtcpu-t194-rce.img.orig
/home/khang/Workspace/Ref/Platforms/Nvidia/Jetson/sdk_install/JetPack_5.1.2_Linux_JETSON_XAVIER_NX_TARGETS/Linux_for_Tegra/bootloader/camera-rtcpu-t194-rce.img

Step 2 : Patch the relevant CSI driver and build the kernel :

diff --git a/kernel/nvidia/drivers/media/platform/tegra/camera/nvcsi/csi5_fops.c b/kernel/nvidia/drivers/media/platform/tegra/camera/nvcsi/csi5_fops.c
index b104ab3eb..f4977142b 100644
--- a/kernel/nvidia/drivers/media/platform/tegra/camera/nvcsi/csi5_fops.c
+++ b/kernel/nvidia/drivers/media/platform/tegra/camera/nvcsi/csi5_fops.c
@@ -219,8 +219,10 @@ static int csi5_stream_set_config(struct tegra_csi_channel *chan, u32 stream_id,
        struct CAPTURE_CONTROL_MSG msg;
        struct nvcsi_brick_config brick_config;
        struct nvcsi_cil_config cil_config;
+       struct nvcsi_error_config error_config;
        u32 phy_mode = read_phy_mode_from_dt(chan);
        bool is_cphy = (phy_mode == CSI_PHY_MODE_CPHY);
+
        dev_dbg(csi->dev, "%s: stream_id=%u, csi_port=%u\n",
                __func__, stream_id, csi_port);
 
@@ -290,6 +292,12 @@ static int csi5_stream_set_config(struct tegra_csi_channel *chan, u32 stream_id,
        else
                cil_config.mipi_clock_rate = csi->clk_freq / 1000;
 
+       /* Error config */
+       memset(&error_config, 0, sizeof(error_config));
+       error_config.stream_intr_mask_lic = 0x3;
+       error_config.stream_intr_mask_hsm = 0x3;
+       error_config.status2vi_notify_mask = 0xFFFF;
+
        /* Set NVCSI stream config */
        memset(&msg, 0, sizeof(msg));
        msg.header.msg_id = CAPTURE_CSI_STREAM_SET_CONFIG_REQ;
@@ -298,6 +306,8 @@ static int csi5_stream_set_config(struct tegra_csi_channel *chan, u32 stream_id,
        msg.csi_stream_set_config_req.csi_port = csi_port;
        msg.csi_stream_set_config_req.brick_config = brick_config;
        msg.csi_stream_set_config_req.cil_config = cil_config;
+       msg.csi_stream_set_config_req.error_config = error_config;
+       msg.csi_stream_set_config_req.config_flags = NVCSI_CONFIG_FLAG_BRICK | NVCSI_CONFIG_FLAG_CIL | NVCSI_CONFIG_FLAG_ERROR;
 
        if (tegra_chan->valid_ports > 1)
                vi_port = (stream_id > 0) ? 1 : 0;

Step 3 : Replace the kernel, module and device-tree manually on the running board. However, there was still following error (similar to prior disabling the CRC check) :

    v4l2-ctl-2929    [001] ....  1281.006004: tegra_channel_close: vi-output, imx219 8-0010
        v4l2-ctl-2929    [001] ....  1281.006123: tegra_channel_set_stream: enable : 0x0
        v4l2-ctl-2929    [001] ....  1281.006125: tegra_channel_set_stream: imx219 8-0010 : 0x0
        v4l2-ctl-2929    [001] ....  1281.006607: tegra_channel_set_stream: 13e10000.host1x:nvcsi@15a00000- : 0x0
        v4l2-ctl-2929    [001] ....  1281.006610: csi_s_stream: enable : 0x0
        v4l2-ctl-2929    [001] ....  1281.010197: tegra_channel_set_power: imx219 8-0010 : 0x0
        v4l2-ctl-2929    [001] ....  1281.010206: camera_common_s_power: status : 0x0
        v4l2-ctl-2929    [001] ....  1281.015671: tegra_channel_set_power: 13e10000.host1x:nvcsi@15a00000- : 0x0
        v4l2-ctl-2929    [001] ....  1281.015674: csi_s_power: enable : 0x0
     kworker/2:0-2752    [002] ....  1281.057644: rtcpu_nvcsi_intr: tstamp:40895916805 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:0-2752    [002] ....  1281.057645: rtcpu_nvcsi_intr: tstamp:40895916805 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:0-2752    [002] ....  1281.057646: rtcpu_nvcsi_intr: tstamp:40895918010 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:0-2752    [002] ....  1281.057646: rtcpu_nvcsi_intr: tstamp:40895918010 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:0-2752    [002] ....  1281.057647: rtcpu_nvcsi_intr: tstamp:40895919213 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:0-2752    [002] ....  1281.057647: rtcpu_nvcsi_intr: tstamp:40895919213 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:0-2752    [002] ....  1281.057648: rtcpu_nvcsi_intr: tstamp:40895920415 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:0-2752    [002] ....  1281.057648: rtcpu_nvcsi_intr: tstamp:40895920415 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:0-2752    [002] ....  1281.057649: rtcpu_nvcsi_intr: tstamp:40895921618 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:0-2752    [002] ....  1281.057649: rtcpu_nvcsi_intr: tstamp:40895921618 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
     kworker/2:0-2752    [002] ....  1281.057650: rtcpu_nvcsi_intr: tstamp:40895922823 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004

It looks like that the CRC check was not disabled at all. I wonder if either the given RCTU firmware or my patch for csi5_fops.c did not work. Could someone help, please ?

Best Regards,
Khang

JerryChang · August 13, 2024, 3:18am

hello khang.l4es,

just double check… would you like to stay-on JP-5.1.2/ r35.4.1 release version for development?
is it possible for moving forward to the latest JP-5 release version for following-up?

khang.l4es · August 13, 2024, 3:29am

Hi @JerryChang,

I would like to stay with JP-5.1.2/ r35.4.1 as most partners’ drivers are aligned with this release.

Best Regards,
Khang

khang.l4es · August 13, 2024, 6:12am

Hi,

By the way, I applied the patch for nvcsi/csi5_fops.c but it is said that the file belongs to Orin : VI cannot recv any data form tc358743 - #13 by ShaneCCC

In case of Xavier NX, is it csi/csi4_fops.c ?

ShaneCCC · August 13, 2024, 6:17am

XNX is csi5_fops.c

khang.l4es · August 13, 2024, 7:50am

So my patch was in the right place, but there’s still no effect.

ShaneCCC · August 13, 2024, 8:46am

Could you dump the REG to confirm the mask?
You may need to disable the firewall to access the REG by devmem utility.
You can search in the forum to disable the firewall.

Thanks

khang.l4es · August 13, 2024, 9:35am

Hi @ShaneCCC,

The only discussion I could find to disable the firewall for accessing the NVCSI register(s) is with Orin family, Can you confirm if this is also available for Xavier NX?

khang.l4es · August 14, 2024, 2:43am

Hi @ShaneCCC,

On the Jetson Xavier NX, I haven’t known yet how to disable the firewall. I followed the relevant discussion to dump the address 0x15a00000 as below :

nvidia@ubuntu:~$ sudo devmem2 0x15a00000
[sudo] password for nvidia:
/dev/mem opened.
Memory mapped at address 0xffffbbd38000.
Value at address 0x15A00000 (0xffffbbd38000): 0x0

Could you help to instruct more about what register(s) you wanted to dump, please ?

khang.l4es · August 14, 2024, 11:03am

Hi again @ShaneCCC,

While waiting for your support to dump the registers of VI/ISP for confirming the CRC disabling, I used v4l2-ctl command to stream data but got :

v4l2-ctl --set-fmt-video=width=3264,height=2464,pixelformat=RG10 --stream-mmap --set-ctrl bypass_mode=0 --stream-count=100 -d /dev/video0


     kworker/0:0-5       [000] ....   481.455616: rtcpu_vinotify_event: tstamp:15885833234 cch:0 vi:0 tag:CHANSEL_NOMATCH channel:0x01 frame:139 vi_tstamp:508338318144 data:0x0000000000000249
     kworker/0:0-5       [000] ....   481.511606: rtcpu_vinotify_error: tstamp:15887059108 cch:0 vi:0 tag:CHANSEL_NOMATCH channel:0x01 frame:140 vi_tstamp:508385853184 data:0x0000000000000249
     kworker/0:0-5       [000] ....   481.511608: rtcpu_vinotify_event: tstamp:15887189273 cch:0 vi:0 tag:FE channel:0x00 frame:139 vi_tstamp:508385822272 data:0x0000000000000020
     kworker/0:0-5       [000] ....   481.511609: rtcpu_vinotify_event: tstamp:15887189434 cch:0 vi:0 tag:FS channel:0x00 frame:140 vi_tstamp:508385851712 data:0x0000000000000010
     kworker/0:0-5       [000] ....   481.511630: rtcpu_vinotify_event: tstamp:15887189576 cch:0 vi:0 tag:CHANSEL_NOMATCH channel:0x01 frame:140 vi_tstamp:508385853184 data:0x0000000000000249
     kworker/0:0-5       [000] ....   481.511632: rtcpu_vinotify_error: tstamp:15888544476 cch:0 vi:0 tag:CHANSEL_NOMATCH channel:0x01 frame:141 vi_tstamp:508433383456 data:0x0000000000000249

Device-tree (of the simulated IMX219) :


                                mclk_khz = "24000";
                                num_lanes = "2";
                                tegra_sinterface = "serial_a";
                                phy_mode = "DPHY";
                                discontinuous_clk = "yes";
                                dpcm_enable = "false";
                                cil_settletime = "0";

                                active_w = "3264";
                                active_h = "2464";
                                mode_type = "bayer";
                                pixel_phase = "rggb";
                                pixel_t = "bayer_rggb";
                                csi_pixel_bit_depth = "10";
                                readout_orientation = "90";
                                line_length = "3448";
                                inherent_gain = "1";
                                mclk_multiplier = "9.33";
                                pix_clk_hz = "182400000";

                                ...

                                embedded_metadata_height = "2";

Best Regards,
Khang

trace_imx219.txt (20.0 KB)

ShaneCCC · August 19, 2024, 4:59am

Here’s the REG.
BTW, if you finally using the argus that couldn’t work by modify the vi5_fops.c due to Argus don’t go this path.

15a10344: NVCSI_STREAM_0_ERR_INTR_MASK_NOVC_0  
15a10270: NVCSI_STREAM_0_INTR_MASK_NOVC_0           
15a18344: NVCSI_STREAM_1_ERR_INTR_MASK_NOVC_0  
15a18270: NVCSI_STREAM_1_INTR_MASK_NOVC_0           
15a20344: NVCSI_STREAM_2_ERR_INTR_MASK_NOVC_0  
15a20270: NVCSI_STREAM_2_INTR_MASK_NOVC_0           
15a28344: NVCSI_STREAM_3_ERR_INTR_MASK_NOVC_0  
15a28270: NVCSI_STREAM_3_INTR_MASK_NOVC_0           
15a30344: NVCSI_STREAM_4_ERR_INTR_MASK_NOVC_0  
15a30270: NVCSI_STREAM_4_INTR_MASK_NOVC_0           
15a38344: NVCSI_STREAM_5_ERR_INTR_MASK_NOVC_0  
15a38270: NVCSI_STREAM_5_INTR_MASK_NOVC_0

khang.l4es · August 19, 2024, 5:01am

Hi,

BTW, if you finally using the argus that couldn’t work by modify the vi5_fops.c due to Argus don’t go this path.

Can you tell what path should I modify ?

ShaneCCC · August 19, 2024, 5:12am

The sources didn’t public to modify to support it.

Thanks

khang.l4es · August 19, 2024, 5:28am

Hi,

Wasn’t it the rce-fw that you shared here Jetpack-5.1.2 - Disable CRC check - #3 by JerryChang?

ShaneCCC · August 19, 2024, 6:21am

Did you verify the RCE firmware?
If yes suppose need special RCE for each release.

khang.l4es · August 19, 2024, 6:29am

Hi @ShaneCCC,

I integrated that firmware, but together with my patch in the initial comment the CRC bypass did not work.
You suggested me to dump the REG (by disabling the firewall protection) but it seems only applicable to the Jetson Orin family while I am working with the Jetson Xavier NX. I also tried devmem2 but the system hung/crashed. Therefore, I haven’t been able to do what you asked me, unfortunately.

ShaneCCC · August 19, 2024, 6:35am

OOPS, looks like Xavier don’t have firewall.
Please launch the camera by vl42-clt and dump the REG by devmem to confirm again.

khang.l4es · August 19, 2024, 6:38am

Hi @ShaneCCC,

OOPS, looks like Xavier don’t have firewall.

Thanks for confirming.

Please launch the camera by vl42-clt and dump the REG by devmem to confirm again.

Is launching v4l2-ctl command prior devmem2 a must to avoid the crash / hang?

ShaneCCC · August 19, 2024, 7:59am

Must open camera then can do the devmem to access the REG.

khang.l4es · September 5, 2024, 4:45am

Hi @ShaneCCC,

I opened the camera with :
$ v4l2-ctl -d /dev/video0 --set-fmt-video=width=1920,height=1080,pixelformat=UYVY --set-ctrl bypass_mode=0 --stream-mmap --stream-count=300

Then tried to read :

nvidia@ubuntu:~$ sudo devmem2 0x15a10230 w
[sudo] password for nvidia: 
/dev/mem opened.
Memory mapped at address 0xffffa1f43000.
Value at address 0x15A10230 (0xffffa1f43230): 0x0

But it gave 0x0 as output.

Other access :

nvidia@ubuntu:~$ sudo devmem2 0x15a10234 w
/dev/mem opened.
Memory mapped at address 0xffffbbbe7000.
Bus error

nvidia@ubuntu:~$ sudo devmem2 0x15a10234 w
/dev/mem opened.
Memory mapped at address 0xffffbe5e8000.
Bus error

nvidia@ubuntu:~$ sudo devmem2 0x15a10238 w
/dev/mem opened.
Memory mapped at address 0xffff8ea53000.
Value at address 0x15A10238 (0xffff8ea53238): 0x0

nvidia@ubuntu:~$ sudo devmem2 0x15a1023c w
/dev/mem opened.
Memory mapped at address 0xffffaab7c000.
Bus error

nvidia@ubuntu:~$ sudo devmem2 0x15a10240 w
/dev/mem opened.
Memory mapped at address 0xffffb63e0000.
Value at address 0x15A10240 (0xffffb63e0240): 0x0

I still need to provide more information to the fpga designer in other discussion as we are struggling with receiving the data from the fpga bridge.

Best regards,
KHang

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Jetpack-5.1.2 - Disabling CRC check does not work

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