Jetpack 6 - UEFI stuck on HspDoorbellEnableChannel: Waiting for HSP Doorbell Channel Enabled

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Orin
1

Hi,

I trying to bring up Jetpack 6.0 on our custom board and hit slight problem.

Board boot up to UEFI, and on UEFI it stays stuck in:

“HspDoorbellEnableChannel: Waiting for HSP Doorbell Channel Enabled.”

CVB eeprom is not present, and it is disabled from MB2 side, but this bit odd. Jetpack 5.1.3 works okay on custom board.

Any suggestions what could cause this ?

4

Hi jsabzk6o,

Are you using Jetpack 6.0 DP(R36.2) or Jetpack 6.0 GA(R36.3)?
Please share the full serial console log for further check.

5

Jetpack 6.0 GA (R36.3).

I’ll get back on this when I have full logs available.

6

Any updates on this issue? I have encountered the same problem. Here is the full output from my boot, up to the HspDoorbellEnableChannel message where it hangs.

full-output-HSPDoorbellErr.txt (127.5 KB)

I believe this problem occurs when I set the “phys” and “phy-names” properties of the PCIe C0 node in the devicetree, as follows:

//
// PCIe (controller C0 in root port mode for MGBE on UPHY2 lane 4)
//
pcie@14180000 {
	status = "okay";
	nvidia,disable-power-down;
	phys = <&p2u_gbe_4>;
	phy-names = "p2u-0";
};

Update: The problem might be related to this issue; I noticed the UPHY “FATAL ERROR” line in my own boot output.

7

I can now confirm that this problem was with the 156.25 MHz clock not being enabled. After this hardware issue was fixed, booting produces the following UEFI error:

full-output-UncorrectableErr.txt (63.8 KB)

Specifically,

Failed to read controller number
PCIE Controller ID-4, Bpmp Phandle-3
ParseGicMsiBase: cannot retrieve property 'msi-parent': FDT_ERR_NOTFOUND
Failed to read controller number
PCIE Controller ID-0, Bpmp Phandle-3
ParseGicMsiBase: cannot retrieve property 'msi-parent': FDT_ERR_NOTFOUND
��ERROR:   Exception reason=0 syndrome=0xbe000011
ERROR:   **************************************
ERROR:   RAS Uncorrectable Error in IOB, base=0xe010000:
ERROR:          Status = 0xec000612
ERROR:   SERR = Error response from slave: 0x12
ERROR:          IERR = CBB Interface Error: 0x6
ERROR:          Overflow (there may be more errors) - Uncorrectable
ERROR:          MISC0 = 0xc44a0040
ERROR:          MISC1 = 0x7cc860000000000
ERROR:          MISC2 = 0x0
ERROR:          MISC3 = 0x0
ERROR:          ADDR = 0x8000000003f600c0
ERROR:   **************************************
ERROR:   sdei_dispatch_event returned -1
ERROR:   **************************************
ERROR:   RAS Uncorrectable Error in ACI, base=0xe01a000:
ERROR:          Status = 0xe8000904
ERROR:   SERR = Assertion failure: 0x4
ERROR:          IERR = FillWrite Error: 0x9
ERROR:          Overflow (there may be more errors) - Uncorrectable
ERROR:          ADDR = 0x8000000003f600c0
ERROR:   **************************************
ERROR:   sdei_dispatch_event returned -1
ERROR:   Powering off core
8

You cannot change the C0 phys that way… Each PCIe controller can only work on specific lane…

Using p2u_gbe_4 to it is inavlid… please read the design guide document.

9

Thank you for the tip; I have referenced the design guide extensively. This table in the AGX Orin bring-up guide is what led me to use p2u_gbe_4 – I need the MGBE functionality of C0.

image
image765×436 17 KB

Can you tell me how to properly configure C0 in the devicetree for 10G MGBE? I already have my ethernet node set up and my ODMDATA variable configured.

10

Hi,

That C0 is for MGBE to use. Not for your PCIe…
MGBE controller and PCIe controller are separate items…

pcie@14180000 {
status = “okay”;
nvidia,disable-power-down;
phys = <&p2u_gbe_4>;
phy-names = “p2u-0”;
};

You don’t need to do this at all. That is what leads your boot failure…
What you are doing here is use a PCIe controller but not a MGBE controller.

12

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