Jetson AGX Orin bring up camera bug

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
1

Hi, I use jetpack 34.1.1, and develop the ar0233-gw5200-max9295 camera driver like jetson agx xavier, but now when I receive the data from camera it failed like below:

[   58.183874] [RCE] NVCSILP clock rate = 408000000 Hz.
[   58.183883] [RCE] VI5: tegra_vi_channel_alloc()
[   58.183884] [RCE] VI5: unit 0 stream ID table:
[   58.183885] [RCE] VI5: unit 0 stream ID table from THI:
[   58.183886] [RCE] VI5: FALCON_CSB_AFBIF_STREAMID_CTL = 0x00
[   58.183887] [RCE] VI5: vi5_trace_enable: configuring trace buffer at iova=0xc55dda00 size=32768
[   58.183888] [RCE] VI5: tegra_vi_channel_alloc: ch=35
[   58.183888] [RCE] VI5: PFSD enabled for channel: NO, expected_count. 0
[   58.183889] [RCE] VI5: channel_submit(35, bfebf000)
[   58.183890] [RCE] VI5: completion_actions[8] size = 30, next offset = 314
[   58.183891] [RCE] VI5: completion_actions[0] size = 31, next offset = 345
[   58.183892] [RCE] VI5: completion_actions[2] size = 14, next offset = 359
[   58.183893] [RCE] VI5: completion_actions[1] size = 30, next offset = 389
[   58.183893] [RCE] VI5: completion_actions[4] size = 14, next offset = 403
[   58.183894] [RCE] VI5: completion_actions[3] size = 14, next offset = 417
[   58.183895] [RCE] VI5: completion_actions[5] size = 2, next offset = 419
[   58.183896] [RCE] VI5: vi5_update_streams: ch=35 stream_mask=0x01
[   58.183897] [RCE] VI5: enabling stream 0
[   58.183897] [RCE] VI5: PFSD enabled for channel: NO, expected_count. 0
[   58.183898] [RCE] VI5: channel_submit(35, bfebf180)
[   58.183899] [RCE] VI5: completion_actions[8] size = 30, next offset = 314
[   58.183900] [RCE] VI5: completion_actions[0] size = 31, next offset = 345
[   58.183901] [RCE] VI5: completion_actions[2] size = 14, next offset = 359
[   58.183901] [RCE] VI5: completion_actions[1] size = 30, next offset = 389
[   58.183902] [RCE] VI5: completion_actions[4] size = 14, next offset = 403
[   58.183904] [RCE] VI5: completion_actions[3] size = 14, next offset = 417
[   58.183905] [RCE] VI5: completion_actions[5] size = 2, next offset = 419
[   58.183906] [RCE] VI5: vi5_update_streams: ch=35 stream_mask=0x01
[   58.196120] bwmgr API not supported
[   58.204980] max9296_read_reg_Dser: i2c read ok, 0x1 = 0x2
[   58.205218] -- jefby Max9296 reg_addr 0x0001=0x2
[   58.205427] max9296_read_reg_Dser: i2c read ok, 0x13 = 0xde
[   58.205543] -- jefby Max9296 reg_addr 0x0013=0xde
[   58.205751] max9296_read_reg_Dser: i2c read ok, 0x6 = 0xdf
[   58.205867] -- jefby Max9296 reg_addr 0x0006=0xdf
[   58.206037] max9296_write_reg_Dser: i2c write ok, 0x2 = 0xf3
[   58.206316] max9295_write_reg_Ser: i2c write ok, slaveAddr 0x80  regAddr 0x2 = 0xf3
[   58.239875] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=0, csi=0)
[   58.239880] [RCE] MIPI clock = 1666666 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
[   58.239884] [RCE] tegra_nvcsi_stream_open(vm0, stream=0, csi=0)
[   58.239887] [RCE] nvcsi_calc_ths_settle ths_settle 48
[   58.239890] [RCE] nvcsi_calc_ths_settle ths_settle 48
[   58.239893] [RCE] nvcsi_calc_ths_settle ths_settle 48
[   58.239896] [RCE] nvcsi_calc_tclk_settle tclk_settle 75
[   58.239900] [RCE] Deskew setup message sent for port 0 num_lane 4
[   60.896021] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[   60.896277] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[   60.897392] (NULL device *): vi_capture_control_message: NULL VI channel received
[   60.897595] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
[   60.897869] (NULL device *): vi_capture_control_message: NULL VI channel received
[   60.898082] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 0
[   60.898505] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[   60.927865] [RCE] VI5: tegra_vi_channel_release(35)
[   60.927868] [RCE] VI5: vi5_channel_disable(35)
[   60.927870] [RCE] VI5: vi5 reset completed in 1 retries
[   60.927872] [RCE] VI5: vi5_update_streams: ch=35 stream_mask=0x00
[   60.927874] [RCE] VI5: disabling stream 0
[   60.927876] [RCE] VI5: tegra_vi_channel_alloc()
[   60.927877] [RCE] VI5: tegra_vi_channel_alloc: ch=35
[   60.927879] [RCE] VI5: PFSD enabled for channel: NO, expected_count. 0
[   60.927881] [RCE] VI5: channel_submit(35, bfebe000)
[   60.927883] [RCE] VI5: completion_actions[8] size = 30, next offset = 314
[   60.927884] [RCE] VI5: completion_actions[0] size = 31, next offset = 345
[   60.927886] [RCE] VI5: completion_actions[2] size = 14, next offset = 359
[   60.927888] [RCE] VI5: completion_actions[1] size = 30, next offset = 389
[   60.927889] [RCE] VI5: completion_actions[4] size = 14, next offset = 403
[   60.927890] [RCE] VI5: completion_actions[3] size = 14, next offset = 417
[   60.927891] [RCE] VI5: completion_actions[5] size = 2, next offset = 419
[   60.927892] [RCE] VI5: vi5_update_streams: ch=35 stream_mask=0x01
[   60.927893] [RCE] VI5: enabling stream 0
[   60.927894] [RCE] VI5: PFSD enabled for channel: NO, expected_count. 0
[   60.927895] [RCE] VI5: channel_submit(35, bfebe180)
[   60.927895] [RCE] VI5: completion_actions[8] size = 30, next offset = 314
[   60.927896] [RCE] VI5: completion_actions[0] size = 31, next offset = 345
[   60.927897] [RCE] VI5: completion_actions[2] size = 14, next offset = 359
[   60.927898] [RCE] VI5: completion_actions[1] size = 30, next offset = 389
[   60.927899] [RCE] VI5: completion_actions[4] size = 14, next offset = 403
[   60.927900] [RCE] VI5: completion_actions[3] size = 14, next offset = 417
[   60.927901] [RCE] VI5: completion_actions[5] size = 2, next offset = 419
[   60.927901] [RCE] VI5: vi5_update_streams: ch=35 stream_mask=0x01
[   63.424419] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[   63.424718] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel
[   63.425427] (NULL device *): vi_capture_control_message: NULL VI channel received
[   63.425649] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_close: Error in closing stream_id=0, csi_port=0
[   63.425945] (NULL device *): vi_capture_control_message: NULL VI channel received
[   63.426170] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_stream_open: VI channel not found for stream- 0 vc- 0
[   63.426929] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: successfully reset the capture channel
[   63.427794] max9296_write_reg_Dser: i2c write ok, 0x2 = 0x3
[   63.428263] max9295_write_reg_Ser: i2c write ok, slaveAddr 0x80  regAddr 0x2 = 0x3
[   63.436955] bwmgr API not supported
[   63.447867] [RCE] VI5: tegra_vi_channel_release(35)
[   63.447983] [RCE] VI5: vi5_channel_disable(35)
[   63.447983] [RCE] VI5: vi5 reset completed in 1 retries
[   63.447985] [RCE] VI5: vi5_update_streams: ch=35 stream_mask=0x00
[   63.447986] [RCE] VI5: disabling stream 0
[   63.447987] [RCE] VI5: tegra_vi_channel_alloc()
[   63.447988] [RCE] VI5: tegra_vi_channel_alloc: ch=35
[   63.447988] [RCE] VI5: tegra_vi_channel_release(35)
[   63.447989] [RCE] VI5: vi5_channel_disable(35)
[   63.447990] [RCE] VI5: vi5 reset completed in 1 retries
[   63.447991] [RCE] VI5: vi5_update_streams: ch=35 stream_mask=0x00

and I changed the rce with url ERROR: NULL VI channel received, VIFALC_TDSTATE. How can I deal with it?

Can you help me? Thanks

2

This is my topo

administrator@administrator-desktop:~/jef$ media-ctl -p /dev/media0
Media controller API version 5.10.65

Media device information
------------------------
driver          tegra-camrtc-ca
model           NVIDIA Tegra Video Input Device
serial
bus info
hw revision     0x3
driver version  5.10.65

Device topology
- entity 1: 13e40000.host1x:nvcsi@15a00000- (2 pads, 2 links)
            type V4L2 subdev subtype Unknown flags 0
            device node name /dev/v4l-subdev0
        pad0: Sink
                <- "ar0233 30-001b":0 [ENABLED]
        pad1: Source
                -> "vi-output, ar0233 30-001b":0 [ENABLED]

- entity 4: ar0233 30-001b (1 pad, 1 link)
            type V4L2 subdev subtype Sensor flags 0
            device node name /dev/v4l-subdev1
        pad0: Source
                [fmt:UYVY8_1X16/1920x1080 field:none colorspace:srgb]
                -> "13e40000.host1x:nvcsi@15a00000-":0 [ENABLED]

- entity 6: vi-output, ar0233 30-001b (1 pad, 1 link)
            type Node subtype V4L flags 0
            device node name /dev/video0
        pad0: Sink
                <- "13e40000.host1x:nvcsi@15a00000-":1 [ENABLED]
4

Please have a check pix_clk_hz/serdes_pix_clk_hz for below Note

https://docs.nvidia.com/jetson/archives/r34.1/DeveloperGuide/text/SD/CameraDevelopment/SensorSoftwareDriverProgramming.html#sensor-pixel-clock

5

Hi @ShaneCCC ,
Thanks very much for your reply. I changed the value it ok now.
But I’m confused about this description.

Note: 
Skew calibration is required if sensor or deserializer is using DPHY, and the output data rate is > 1.5Gbps.
An initiation deskew signal should be sent by sensor or deserializer to perform the skew calibration. If the deskew signals is not sent, the receiver will stall, and the capture will time out.
You can calculate the output data rate with the following equation:

* Output data rate = (sensor or deserializer pixel clock in hertz) * (bits per pixel) / (number of CSI lanes)

How to implement send the deskew signal? I use MAX9296A as deser

By the way, Does Jetson Xavier not have to do this?

6

It’s J5.0 DPHY configure with Xavier or Orin
Please consult with sensor vendor for the deskew signal. Suppose It’s MIPI spec.

7

OK，Thanks very much

9

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