Jetson AGX Orin Capture Error PHY_INTR0

FYI,
the interrupt status 0x40, is toggle by intr_cil_data_lane_sot_mb_err1_b.
as mentioned, this is error due to more than one bit error detected on the lane [A/B] sync word. where the “_b” at the end means its lane B.
so, it’s due to sync words have errors.

could you please double check the data-rate, don’t you mentioned it’s 4-lane config in the beginning?