Jetson AGX Orin CSI capture timeout — MIPI data lanes active but clock lane flat (MAX96724R GMSL2)

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
1

Hey folks,

I am not able to capture the sensor image using the MAX96717R and MAX96724R serializer and deserializer boards in a GMSL setup interfacing with the AP1302 ISP/AR0234 sensor.

Hardware:

  • Jetson AGX Orin, JetPack 6.0 / L4T 36.3
  • MAX96724R deserializer → serial_d / port-index 3
  • AP1302 ISP, 2-lane DPHY tunnel mode, YUV422

Symptom:
v4l2-ctl capture times out with:
tegra-camrtc-capture-vi: uncorr_err: request timed out after 2500ms

Logic analyzer shows:

  • DES D0P (DA0): active data bursts ✅
  • DES D1P (DA1): active data bursts ✅
  • DES CKAP (clock lane): completely flat ❌

SerDes confirmed working:

  • VID_LOCK = 0x62 ✅
  • 2(1x4) D-PHY mode, 900 Mbps, discontinuous clock

DTS:

  • tegra_sinterface = “serial_d”, port-index = 3
  • bus-width = 2, data-lanes = <0 1>
  • link-frequencies = 1000000000

The GMSL2 tunnel is working end to end but the Jetson CSI PHY sees no clock. Is there a known issue with MIPI clock output on serial_d with JetPack 6.0, or any additional register/DTS settings needed to enable the clock lane?

I am attaching the below files:

  1. Snapshot of the clk and data waveforms for the serializer and deserializer

  2. dmesg log file

  3. trace log file

serdes_clk_data_waveforms
serdes_clk_data_waveforms1635×490 67.2 KB

camera_dmesg_full.log (66.3 KB)

camera_trace.log (8.7 KB)

I would appreciate any pointers to resolve this problem. Thanks!

4

The MIPI clock is control by the GMSL, suppose it could be GMSL config or HW problem.

Thanks