Jetson AGX Orin Custom Carrier Board – Boot Delay and No DP Output

[saikiran.s]

Hi Everyone,

We have designed a custom carrier board for the Jetson AGX Orin module based on the P3737 reference design. We have closely followed the concept schematics and implemented the components accordingly.

The SoM is able to boot successfully on our carrier board; however, we are facing the following issues:

1. Boot delay: The system takes significantly longer (~1 minute more) to boot compared to the Jetson AGX Orin Developer Kit.

2. DisplayPort output not working: We are not getting any display output via DP, even after full system boot.

[carolyuu]

*** Please note that this reply is generated by LLM automatically ***

Based on the provided context, I’ll address the issues you’re facing with your custom carrier board for the Jetson AGX Orin module.

Issue 1: Longer boot time

The boot time of your custom carrier board is significantly longer (1 minute more) compared to the Jetson AGX Orin Developer Kit. This could be due to several reasons:

• Device tree configuration: The device tree configuration might not be optimized for your custom carrier board. The Jetson AGX Orin Developer Kit has a pre-configured device tree that is optimized for its specific hardware. You may need to modify the device tree configuration to match your custom carrier board’s hardware.
• Kernel configuration: The kernel configuration might not be optimized for your custom carrier board. The Jetson AGX Orin Developer Kit has a pre-configured kernel that is optimized for its specific hardware. You may need to modify the kernel configuration to match your custom carrier board’s hardware.
• Firmware loading: The firmware loading process might be taking longer on your custom carrier board. You can try to optimize the firmware loading process or use a different firmware loading mechanism.

Issue 2: No display output via DP

You’re not getting any display output via DP even after full system boot. This could be due to several reasons:

• Display controller configuration: The display controller configuration might not be correct for your custom carrier board. The Jetson AGX Orin Developer Kit has a pre-configured display controller configuration that is optimized for its specific hardware. You may need to modify the display controller configuration to match your custom carrier board’s hardware.
• DP port configuration: The DP port configuration might not be correct for your custom carrier board. You may need to modify the DP port configuration to match your custom carrier board’s hardware.
• Firmware issues: Firmware issues might be preventing the display output via DP. You can try to update the firmware or use a different firmware version.

Comparison with Jetson Orin Nano

The Jetson Orin Nano is a different module compared to the Jetson AGX Orin. While the Jetson Orin Nano has a similar architecture, it has different hardware components and configurations. Therefore, the issues you’re facing with your custom carrier board for the Jetson AGX Orin module might not be directly applicable to the Jetson Orin Nano.

However, if you’re planning to design a custom carrier board for the Jetson Orin Nano, you can follow similar steps to optimize the device tree configuration, kernel configuration, and firmware loading process. Additionally, you’ll need to ensure that the display controller configuration and DP port configuration are correct for the Jetson Orin Nano.

Recommendations

To resolve the issues with your custom carrier board for the Jetson AGX Orin module, I recommend the following:

• Review the device tree configuration and kernel configuration to ensure they are optimized for your custom carrier board’s hardware.
• Modify the display controller configuration and DP port configuration to match your custom carrier board’s hardware.
• Optimize the firmware loading process or use a different firmware loading mechanism.
• Update the firmware to the latest version or try a different firmware version.

If you’re planning to design a custom carrier board for the Jetson Orin Nano, follow similar steps to optimize the device tree configuration, kernel configuration, and firmware loading process. Additionally, ensure that the display controller configuration and DP port configuration are correct for the Jetson Orin Nano.

*** Please give the thumbs up if you get answers you like. Or provide feedback to help us improve the answer. ***

[saikiran.s]

Since our carrier board is designed exactly the same as the P3737 reference design, is it still necessary to modify the device tree and kernel configurations?

[saikiran.s]

Hi,

I am attaching the UART3 log data. Kindly review it and let me know if there are any issues.

Jetson_AGX_Orin_UART_log.txt (272.8 KB)

[WayneWWW]

I am not sure why so many users really like to say their board is same as p3737 but give out a log that has obvious different things from p3737.

If you don’t have some interfaces, disable it from the device tree.

Also, it is not able boot delay. Your whole system just reboot multiple times. Every time is seems got stuck in UEFI. Confirm that first.

[WayneWWW]

Also, you and your team don’t need to file 2 duplicated topics.

Jetson Orin's DP Output is not Functional

All the necessary drivers are there and no error in boot log. Check what pinmux got flashed to your board. If you are sure that is default one, then please really go back to review your hardware design or measure hardware signal. We’ve heard lots of users telling they are using same design as devkit. But most of them turned out have some mistakes there.

[saikiran.s]

I sincerely apologize for this. I had informed my team that they would not be continuing the topic from that account.

[saikiran.s]

Actually, I will Explain Entire scenario what happen from design face of carrier board,

1. we have followed the design files of p3737.

   Custom board Carrier Board Schematic.pdf (1.2 MB)

2. However, in that we did not get the DNP components, from the forums reference got to the concept schematics for the DNP components. so, we have removed DNP components from the PCB.

   P3737_A05_Concept_schematics.pdf (968.2 KB)

3. then we got to know that Button MCU need to flash by provided button MCU firmware. we did and added jumper to Automation header J42, pin 5 and 6 to auto startup.

4. Debug MCU has been unmounted.

5. from the SOM which is there on the Dev kit P3730 , we have unplugged and plugged to our custom carrier board.

6. when we power ON the system, we are able to see the all voltages SYS_VIN_HV, SYS_VIN_MV, SYS_VIN_SV, VDD_5V, VIN_POWER_ON, MODULE_POWER_ON, CARRIER_POWER_ON signals.

7. so, we have connected DP monitor to get the display output from the system. But not getting any output on screen.

8. so, we thought to check the UART3_debug_log , from here we got to know that SOM is booting, with some delay (after multiple boot trys), getting log in prompt.

kindly take these inputs as reference, please let me know any information required

[WayneWWW]

I already told something on your old account post. please check if your hotplug will trigger any new log in xorg log. if it does not, and if your pinmux is correct, then this is likely your hardware issue.

Check your signal on hpd and dpaux signal too.

[saikiran.s]

I performed a hotplug test on the DisplayPort, and I’ve attached the corresponding Xorg.0.log output for your reference.

With_display_connected_uart_log.txt (95.5 KB)

Xorg_log_with_display_connected_and_hot_pluging.txt (42.7 KB)

Additionally, I have verified the HPD and DP_PWR signals:

• The HPD line goes high as expected when the DisplayPort cable is connected.

• DP_PWR is stable and present during the connection.

Even, we want to know how to disable the Unused Interface, How to disable in the device tree.

we did not use MGBE interface, from UART i saw that system is waiting that point for more time, while booting.

[WayneWWW]

20.779] (–) NVIDIA(GPU-0): DFP-0: disconnected
[ 20.779] (–) NVIDIA(GPU-0): DFP-0: Internal DisplayPort
[ 20.779] (–) NVIDIA(GPU-0): DFP-0: 2380.0 MHz maximum pixel clock
[ 20.779] (–) NVIDIA(GPU-0):
[ 20.805] (–) NVIDIA(GPU-0): DFP-1: disconnected
[ 20.805] (–) NVIDIA(GPU-0): DFP-1: Internal TMDS
[ 20.805] (–) NVIDIA(GPU-0): DFP-1: 165.0 MHz maximum pixel clock
[ 20.805] (–) NVIDIA(GPU-0):

I still see no display connected here. What pinmux are you flashing to the board? Or you don’t know what you are doing here?

Have you measured the signal on DPAUX?

You could refer to adaptation guide first. Disable the etherent node on 6810000 in your device tree and reflash the board then both UEFI and kernel side will have disabled MGBE

Jetson Module Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide 1...

[saikiran.s]

Hi,

@WayneWWW

I still see no display connected here. What pinmux are you flashing to the board? Or you don’t know what you are doing here?

We have purchased the Jetson AGX Orin SOM (64GB) module, which came without an OS. We installed JetPack 5.0 using SDK Manager without modifying any settings.

We did not change the pinmux before flashing the SOM because our carrier board design follows the P3737 reference schematics exactly, without changes to the pin assignments. Some interfaces, such as MGBE, have been removed since we are not planning to use them.

@WayneWWW

Have you measured the signal on DPAUX?

No, What should we expect if we measure the DPAUX signals?
I will take the measurements and share the results tomorrow.

@WayneWWW

You could refer to adaptation guide first. Disable the etherent node on 6810000 in your device tree and reflash the board then both UEFI and kernel side will have disabled MGBE

Before posting my query on the forum, I went through these pages, but I am not sure where to start. I am also not sure how to disable the device tree overlays.

When flashing the SOM from the SDK Manager on the host PC, all packages are downloaded to the host system. need to modify them as required and then flash the modified version?

I am very new to working with this module, so I kindly request your help in resolving this display issue.

thanks in advance

[WayneWWW]

Jetpack5.0 does not support Orin AGX 64GB. I hope you are talking about something like Jetpack5.1.3 but not really “5.0”.

If you are using sdkmanager to flash, then the pinmux should be also fine. I am pretty sure your hardware has problem in this situation.

As for device tree, you could file a new topic for it. I don’t think that really matters to your DP.

[saikiran.s]

@WayneWWW

Jetpack5.0 does not support Orin AGX 64GB. I hope you are talking about something like Jetpack5.1.3 but not really “5.0”.

yeah, ofcourse Jetpack5.1.3

@WayneWWW

If you are using sdkmanager to flash, then the pinmux should be also fine. I am pretty sure your hardware has problem in this situation.

I have checked everything for continuity, and it seems to be fine as per the schematics. even HPD signal is coming ON board of Connect Display port of monitor.

i got to know that 3v3_DP_EN is not coming from SOM, so I mounted R309 and removed R586. so, getting DP_POWER.

@WayneWWW

As for device tree, you could file a new topic for it. I don’t think that really matters to your DP.

sure.

[saikiran.s]

Hello,

The HPD signal and 3V3_DP_EN are coming from the SOM, but the display signal is not coming up. I am able to see the boot logs over the terminal using the UART3_DEBUG pins.

On the SOM, I have disabled the EEPROM.

Thanks,

[saikiran.s]

any help!, we did not change the pin assignment for the DP on the Carrier board we have designed, design is same as the Dev kit, i have inspected All voltages are okay, is there any concern to check DP to work,

with the same SOM display is coming dev kit, what we have purchased for reference P3730.

with our carrier board only it is not working. is there any DP related hardware to check for the troublesooting like TVS diode IC D5

[WayneWWW]

1. am able to see the boot logs over the terminal using the UART3_DEBUG pins.

Please use uart to access the board and share me the xorg log.

2. On the SOM, I have disabled the EEPROM.

I am not sure what does that mean here. The EEPROM on SOM could not be disabled. It will affect the function. You could ignore CVB eeprom but you could not disble CVM eeprom.

[saikiran.s]

@WayneWWW

Please use uart to access the board and share me the xorg log.

xorg.txt (18.1 KB)

please find the boot log also
Jetson_boot_uart_log.txt (90.8 KB)

these are took, when display is connected time only.

@WayneWWW

I am not sure what does that mean here. The EEPROM on SOM could not be disabled. It will affect the function. You could ignore CVB eeprom but you could not disble CVM eeprom.

i did this, i have modified that line and reflashed jetson linux. , if i did not do these, booting is structed somewhere in the failed to read EEPROM.

[WayneWWW]

Just to make sure. Do you really have DP monitor connected when you dump this xorg log?

I saw it shows disconnected.

[ 17.310] (–) NVIDIA(GPU-0): DFP-0: disconnected
[ 17.310] (–) NVIDIA(GPU-0): DFP-0: Internal DisplayPort
[ 17.310] (–) NVIDIA(GPU-0): DFP-0: 2380.0 MHz maximum pixel clock

[saikiran.s]

@WayneWWW

Do you really have DP monitor connected when you dump this xorg log?

i have connected ,

good newz, wow, display port is working now.
i did some soldering touchup.
thanks for your help on this.

SAI KIRAN