Hi, NVIDIA Jetson Team:
I am currently using Arm Development Studio 2024.1 with the DStream-ST debugger to debug and trace the Nvidia AGX Orin 32GB Development KIT（Official）. I am now able to perform single-step debugging and can trace to the ETF (128 KiB).
Now I would like to trace to DDR memory through the ETR. How should this be configured?
The JetPack version is R36.5.
The AGX Orin TRM mentions:
DRAM
Capacity is determined by platform ETR is used to to convert ATB traffic to AXI traffic and streamed via DBB to a GSC carveout. ETR has a dedicated GSC assigned to dump its trace in memory.
Typically used when Connection to off-chip TPA is unavailable or has insufficient bandwidth
Traffic to DRAM can accommodate trace bandwidth
Trace does not fit in ETF.
Tracing to DRAM using ETR
ETR has a dedicated GSC (GSC#15). The size and location of the carveout is based on BCT and can be derived based on the GSC’s BOM and SIZE registers.
ETR performance bandwidth requirements necessitate SMMU bypass. However, per security
guidelines, accesses that bypass SMMU fall into a GSC. Hence, for performance purposes, ETR
needs a GSC. Also, using GSC for ETR traces enables restricting accesses to trace information and avoids on-chip malicious code from snooping trace information.
ETR is categorized as a boot client by MSS. This has an implication that ETRW (ETR write client)
PCFIFO interlock is enabled
(MC_PCFIFO_CLIENT_CONFIG4_0[PCFIFO_ETRW_ORDERED_CLIENT]=ORDERED) by default out of reset. Software default for this is PCFIFO_ETRW_ORDERED_CLIENT=UNORDERED.
PCFIFO_ETRW_ORDERED_CLIENT is programmed to UNORDERED for improved ETR DRAM
bandwidth.
To ensure ETR maximizes data throughput, program ETR as follows:
AXCTL[CacheCtrl0]=AXCTL[CacheCtrl1]=1 (enable buffering and modifiability attributes)
AXCTL[CacheCtrl2]=AXCTL[CacheCtrl3]=0 (Write-allocate cache does not need to be enabled, as caching does not help ETR write pattern, which skims across the entire range of write-range, which exceeds maximum size of cache)
WrBurstLen=0xF (maximum burst length)
ScatterGatherMode=0 (avoid scatter-gather mode)
RSZ: This is the ETR’s target buffer size in DRAM. Recommend values greater than 0x8000.
Do not use value less than 0x8000 (128KiB) because, in that case, ETF (128KiB) could be used
as a circular buffer instead of streaming to DRAM.
ETR to DRAM throughput is 5.5GB/s.
The Linux Development Guide mentions:
Miscellaneous Configuration — NVIDIA Jetson Linux Developer Guide
I have modified the device tree file in the bootloader and linux kernel:
bootloader/tegra234-mb1-bct-misc-p3701-0000.dts：
bootloader/tegra234-mb1-bct-carveout-l4t.dtsi
Arm development studio configuration is below.
But it cannot work! When I stop the trace it WARN belowed:
And Cannot Stop the core，then the core seems to be Hung.
Specifically, how should the bootloader-related configuration be set in order to achieve this?
Thanks.