【Jetson AGX Orin】How to config to trace to system RAM using Coresight with ETR in Arm Development Studio by Arm DStream debugger?

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
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You don’t need to change “everything” in boot; the key is to set up GSC15 + the ETR MC control registers correctly in the MB1 BCT. Based on the Jetson docs and the internal ETR enablement work for T234, here is what you should do.

1. SDRAM BCT: define the GSC15 carveout for ETR

Edit your SDRAM BCT (the memcfg / SDRAM .dtsi that tegra234-mb1-bct-carveout-l4t.dtsi feeds into) so that GSC#15 exists and has enough size:

  1. In the SDRAM configuration BCT, make sure fields for GSC15 are set (names from the docs):

    • McGeneralizedCarveout15Bom / McGeneralizedCarveout15BomHi

      • Recommended: set both to 0 so MB1 is free to choose a suitable base address.

    • McGeneralizedCarveout15Size128kb

      • Set this so the total size ≥ the trace buffer you want.

      • Size is encoded as in the doc (128 KiB and 4 KiB granularity fields); for a few MB buffer, pick a value that yields e.g. 4 MiB–32 MiB.

  2. In MB1 platform config (same BCT family), set an alignment for GSC15 in the carveout block (pattern is shown for other GSCs):

    carveout.gsc[15].alignment = 0x100000;    # 1 MiB alignment (typical)

  3. Rebuild BCT and flash. On boot, check early MB1 logs for a line like:

    allocated(CO:15) base:0xXXXXXXXXX size:0xYYYYYY

    That base and size are what you must use in Arm DS as the ETR buffer address/length.

2. MB1 “misc” BCT: program ETR’s MC write/read control and allow GSC15 access

In tegra234-mb1-bct-misc-p3701-0000.dts (or equivalent), ensure the coresight block programs the ETR MC registers:

  1. Use the MB1 BCT fields for ETR:

    coresight.cfg_etr_mc_wr_ctrl = <0x0000007F>;   # ETR_SID = 0x7F
coresight.cfg_etr_mc_rd_ctrl = <0x0000007F>;   # usually same SID for reads

    • Per the T234 ETR support bug, there are two valid SID modes:

      • ETR_SID = 0x7F → ETR accesses GSC15 directly with SMMU bypass (what the TRM recommends for max bandwidth).

      • ETR_SID = TEGRA_SID_NISO0_ETR → ETR goes through SMMU to non-GSC memory.

    • For the “ETR → dedicated GSC” path described in the TRM, use 0x7F.

  2. Disable “force internal” for the ETR client on GSC15 so that writes can reach DRAM instead of faulting as GSC violations. In the MC security BCT for carveout 15 (names are from the internal ETR/PTM note):

    • Ensure the bits corresponding to:

      • CARVEOUT15_FORCE_INTERNAL_ETRW

      • CARVEOUT15_FORCE_INTERNAL_ETRR are set to 0 (DISABLE) in the GSC15 force-internal register (MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS4_0 in TRM notation).

    • There is a companion internal bug that explicitly asks to “disable GSC15 force_internal in the carveout BCT” for ETR use.

  3. Rebuild MB1 BCT, re-flash, and confirm:

    • You no longer see MC errors like csw_etrw: GSC access violation or csw_etrw: MC request violates VPR requirements in Linux logs when tracing.

    • CO:15 allocation line is present and matches your expectations.

3. (Optional but recommended) Kernel DT / driver side

Even if you’re primarily using DSTREAM as an external debugger, it’s best if the Linux BSP is consistent with this setup:

  1. In the kernel device tree for the ETR node, add SMMU mapping if you ever use it from Linux:

    tmc_etr0: tmc-etr@... {
    ...
    iommus = <&smmu_niso0 TEGRA_SID_NISO0_ETR>;
    dma-ranges = ...;   // as in the upstream patch
};

  2. Make sure the ETR driver uses a 32-bit DMA mask as per the internal patch (SMMU only supports up to 39-bit IOVA on this path).

These are the same changes used for the in-kernel “ETR as PTM sink” setup on Jetson.

4. Arm Development Studio / DSTREAM settings

Once MB1 and SDRAM BCT are fixed:

  1. In Arm DS, configure the ETR sink as:

    • Type: System RAM (memory-backed).

    • Base address: the base printed for CO:15 (from MB1 logs).

    • Buffer size: ≤ GSC15 size (from the same line).

    • Other knobs matching TRM recommendations (already in your post):

      • WrBurstLen = 0xF

      • ScatterGatherMode = 0

      • RSZ ≥ 0x8000 (128 KiB)

      • CacheCtrl0/1 = 1, CacheCtrl2/3 = 0.

  2. With the above BCT changes, stopping the trace should no longer hang the core, because ETR writes now hit a valid, writable GSC15 DRAM region instead of causing MC/GSC faults (which is what the internal debug notes show when things are mis-configured).

If you align your SDRAM carveout for GSC15, GSC15 force-internal bits, and coresight.cfg_etr_mc_* SIDs exactly as above, you’ll have the bootloader side correctly set up for tracing from ETR to system RAM on Jetson AGX Orin.