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To address your questions and provide a comprehensive answer, we’ll break down the process into steps, comparing and contrasting where necessary, and providing detailed explanations.
Understanding the GPIO Number
First, you’ve identified the GPIO number as 388 for the pin soc_gpio18_pg5. This is crucial because it allows you to find the specific MMIO addresses for controlling this GPIO.
Finding the Base MMIO Address
The base MMIO address of the GPIO controller can be found in the kernel boot log or through the use of gpio debugfs. For the Jetson AGX Orin, the base address for the GPIO controller is typically noted in the kernel boot log as tegra234-gpio at base index 348. This value is specific to the Tegra234 SoC used in the Jetson AGX Orin.
Calculating the Pin Number and Understanding the GPIO Controller
You’ve already calculated the pin number using the formula base + port_offset + pin_offset, which resulted in GPIO number 388 for soc_gpio18_pg5. This calculation is essential for navigating the GPIO controller’s register space.
MMIO Address for the GPIO
The MMIO address for a specific GPIO pin can be calculated by adding the base address of the GPIO controller to the offset of the register that controls the pin. For Tegra SoCs, the GPIO registers are typically laid out in a specific pattern:
- The output register for a GPIO is usually at an offset of
0x00 from the base address of the GPIO bank that the pin belongs to.
- Given that the GPIO number is 388, and assuming a standard 32-bit register width, you would first need to determine which GPIO bank this pin belongs to. The Tegra234 GPIO controller is divided into banks, each controlling a range of GPIOs.
- The offset within the bank for the output register of a specific GPIO can be calculated or looked up from the datasheet or reference manual. However, the exact offset might depend on the specific SoC and its configuration.
Expected Values for Low or High Output
When reading or writing to the output register for a GPIO, the expected values depend on the configuration of the pin:
- Low Output: Typically, setting the corresponding bit in the output register to
0 will set the pin to a low output.
- High Output: Setting the bit to
1 will set the pin to a high output.
However, the actual bit-to-pin mapping and the behavior (e.g., open-drain vs. push-pull) depend on the pin’s configuration, which can be set using the pinmux as you’ve done.
Documentation and References
The lack of clear documentation in the datasheet or TRM (Technical Reference Manual) for specific MMIO addresses and register maps is not uncommon. SoC vendors like NVIDIA often provide detailed documentation, but the complexity and customization options of these devices mean that not all information can be easily found in a single document.
For the Jetson AGX Orin and other Tegra-based devices, NVIDIA provides various resources, including the TRM, datasheets, and developer forums, which can be invaluable for finding the necessary information. Additionally, the Linux kernel source code and device tree files can provide insights into how the hardware is configured and accessed.
JetPack and L4T Versions
You’re using JetPack 6.0 / L4T R36.4.3 on Jetson AGX Orin. These versions are specific and might have their own set of documentation, patches, or known issues that could affect how GPIOs are accessed or configured. Always refer to the latest documentation and release notes for your specific version of JetPack and L4T.
Conclusion
To verify your configuration and read the MMIO registers directly for soc_gpio18_pg5 (GPIO 388), you would:
- Find the Base Address: Confirm the base MMIO address of the GPIO controller from the kernel boot log or
gpio debugfs.
- Calculate the Offset: Determine the offset within the GPIO bank for the output register of GPIO 388.
- Read/Write the Register: Use the calculated MMIO address to read or write the output register, setting the pin high or low as needed.
- Consult Documentation: Refer to the Tegra234 TRM, Jetson AGX Orin documentation, and Linux kernel documentation for detailed information on GPIO configuration and access.
Given the complexity and the specificity of the question, direct calculation or lookup from provided documents might not yield the exact MMIO address without additional context or clarification on the GPIO bank structure and register layout of the Tegra234 SoC.
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