We are seeking how to access the JTAG debug interface on the Orin platform. We need this to be able to debug our OS and hypervisor, as well as getting off-chip execution traces to study the actual timing properties of some part of the code.
So far, we can connect our debugger(lauterbach) to the JTAG port, get the SoC IDCODE, but then nothing, we cannot dump the Debug Access Point (DAP), which would give us the debug configuration to use to access CoreSight resources.
We have seen in the documentation available on the nvidia website that there are 2 signals, NVJTAG_SEL and NVDBG_SEL. They seem to concern JTAG, but we can’t find any solid information on how to use them.
Where are these signals accessible (pins on the board?)? What would be their values to enable JTAG debugging?
If you could share any kind of information that could allow us to reach the DAP and unlock JTAG access, that would be nice.
In the Xavier TRM, there is one hit “trace port analyzer (TPA) like DSTREAM over the Trace Port Interface Unit (TPIU)”, where the TPIU in (Fig. 8.33) is sent to SDMMC1, which I believe to be the SD card slot. Is there a particular formatting for the sd card? does it need to be mounted on the system? Is it the hardware copying the data straight to the card (from the ETF), or does it go by the OS?
So from your very short answer, should I assume that it is the same debug system that is available on the Orin as in the Xavier?
The Orin TRM version Orin-TRM_DP10508002_v1.0p from 2022-03-24, has no mention of the DFD that you have in the Xavier. Therefore, could you update the manual?
the Xavier ROM table is accessible through the chip and in the TRM, and therefore we can have the configuration of the different coresight elements, but we don’t have this level of information for Orin. And so I can’t have the address to stop/resume cores, stop/resume trace. Any hint on that?