Jetson AGX Orin x2 PCIe Isolation

[acaravantesnov]

Good afternoon,

My doubt is related to the isolator shown on the Jetson AGX Orin Design Guide when communicating 2 Jetsons via PCIe (image attached).

Is the isolation of those 4 signals due to something in particular, or is it just because it is assuming both Jetsons are powered through 2 different 3V3DC supply voltages?

Thank you in advance.

[carolyuu]

Hi,

If you are designing a custom base board, then it means some adaptation configurations are needed.
Otherwise, your board may not work fine.

For Orin AGX series, you could refer to below document
https://docs.nvidia.com/jetson/archives/r36.3/DeveloperGuide/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=universal%20serial%20bus#jetson-agx-orin-platform-adaptation-and-bring-up
(please be aware that above link is for rel-36.3/jetpack6.0)

This document includes below configuration

1. pinmux change & GPIO configuration
2. EEPROM change as most custom boards do not have an EEPROM on it.
3. Kernel porting
4. PCIe configuration
5. USB configuration
6. MGBE configuration
7. RGMII configuration

Thanks!

[Trumany]

It is to isolate power rails of RP and EP.