Jetson AGX Xavier CS and Clock Cycle configuration

Hello,

I am working on SPI communication from Jetson AGX Xavier(Host) to TI Radar Device(Slave).

I have the following requirement and I do not know how to configure them on Jetson AGX Xavier.

  1. Host should ensure that there is a delay of at least 2 SPI clocks between CS going low and start of SPI clock
  2. Host should ensure that CS is toggled for every 16 bits of transfer via SPI
  3. There should be a delay of at least 2 SPI Clocks between consecutive CS
  4. SPI needs to be operated at Mode 0 (Phase 1, Polarity 0)
  5. SPI word length should be 16 bit (Half word)

Note : I am currently using ioctl commands from userspace for SPI access.
Since I am new to working on Jetson AGX, kindly advice on the how to proceed with the configuration.

Thanks and Regards
Vignesh

We will investigste this issue to give the update soon. Thanks