Hello!
I’m currently working to implement memory bandwidth management policies on the Jetson AGX Xavier platform. In the Technical Reference Manual (TRM), I found references to DDA_{…} QoS management registers, which are controlled by the NVGINDEX/NVGDATA system register interface. The latest version of the TRM (v1.4, published in 2020) states that a description of such registers will be provided in future releases.
Where can I find documentation about such registers?
Thanks