Hello, I made a PCB carrier board, and led the PCIE interface in the module out of some external devices, and found that the PCIE device could not be recognized after returning to the board, and found that the CLK and REST of the PCIE interface were not connected to TX/RX. UPHY0 does not use the C1 clock, and like this, the clock and reset do not correspond. Using the oscilloscope measurement, it is found that after powering on, the module performs the PCIE device handshake in the port order, and whether there is a way to modify the PCIE settings in the kernel source code so that the reset signal of all PCIE PORTS is sent consistently, the clock signal is sent consistently, and the handshake signal is consistent. And regardless of whether the handshake is successful, the reset signal and clock signal of all channels are continuously maintained.
You need to follow our reference carrier board design and/or the design guide to ensure the correct PCIe clocks and reset signals for the corresponding PCIe interface instances are being routed/connected. Mixing of PCIe clocks signals and reset signals between PCIe controllers will not work, if I understood your question correctly.
The situation is as you understand it. In the current state, can we avoid the problem of PCIE handshake failure by configuring PCIE startup? My understanding is that when the module starts, configure RST for all PCIE PORTs, CLK, and handshake signals to be turned on simultaneously. Then maintain all signals regardless of whether the handshake is successful or not. How to modify the configuration file in this way? Thank you
Alternatively, in the current configuration, set all RST.CLK to persist after startup, and then add the PCIE handshake command again at the end
Are you talking about the hardware is mixed up and wrong? If so, then we don’t support this thing. No software could save your case.
Thank you, I can perform fly wire processing, and I have seen from other posts that resetting and clock persistence can be set. This can be configured, right? I want to keep PCIE’s RST and CLK persistent. How can I configure this?
You should tell whether you are using Jetpack4 or Jetpack5 first.
Jetpack? The installation package version I downloaded from the official website is linux-tergra-r3251.
And the file path I found is (Linux_for_Tegra/source/public/hardware/nvidia/platform/t19x/galen/kernel-dts/common) tegra 194-p2888-0000-a00.dtsi
I am responsible for generating system image files and then using USB to flash and burn the system
Rel-32.x means it is from Jetpack4.
Jetpack4 are all rel-32.x release and Jetpack5 are all rel-35.x release.
Please remember that so that the communication would be more efficient.
If ti is Jetpack4, then I think you already do the modification correctly.
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