Hello,
We’re attempting to use the THS0 UART port to communicate with an IMU. The received packets are timestamped, and we’re seeing non-deterministic RX behavior. Curious as to how the UART peripheral in the BSP is actually configured (FIFO triggered DMA, TX complete DMA, etc.). Also, is there a separate scheduler for processing DMA’d packets similar to how USB is handled?
hello alexander35 ,
it’s software to register as ttyTHS*, you may see $ dmesg | grep THS, for the mappings of serial ports.
please access Xavier Product Design Guide via download center for reference.
you may check Chapter-13.3 for the details of UART, for example, UART pin description and also UART connections,
BTW,
the default baudrate settings is 115200/8n1, you’ll also check L4T Driver Package (BSP) Sources for device tree definitions.
thanks
i.e. $L4T_Sources/r32.5.1/Linux_for_Tegra/source/public/hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-uart.dtsi