Jetson-io fatal error

Hi,
I tried to use the jetson-io package to configure the 40pin header but immediately encounter error as shown in screenshot below. jetson-io complains about touch_clk_pcc4. I think it’s related to changes made to enable the SPE gpio app.

Is there way to get this working and use jetson-io with the SPE configuration changes?

Hello, teemu1:
I’m not sure about your operations.
If you want to operate GPIO from SPE firmware, please follow instructions in GPIO doc of SPE package. In that case, CCPLEX (Linux) cannot access those pins anymore.

Generally, the module can only be controlled by one entity, either SPE R5, or CCPLEX.

br
ChenJian

I’m not trying to use the same pin for both SPE and Linux. I’ve done the changes to use a pin from SPE and now want to use some another pin from Linux side for something unrelated. However looks like the SPE change somehow broke the jetson-io tool?

These are the changes I made as documented in the SPE GPIO example.

tegra194-mb1-bct-scr-cbb-mini-p3668.cfg:
  scr.49.6 = 0x18001010; # GPIO_CC_SCR_04_0
  scr.53.6 = 0x18001010; # GPIO_DD_SCR_00_0

tegra194-mb1-bct-gpioint-p3668-0001-a00.cfg:
  gpio-intmap.port.CC.pin.4 = 2; # GPIO CC4 to INT2
  gpio-intmap.port.DD.pin.0 = 2; # GPIO DD0 to INT2

tegra19x-mb1-pinmux-p3668-a01.cfg:
  pinmux.0x0c302000 = 0x00000025; # touch_clk_pcc4: GPIO, pull-down, input-disable
  pinmux.0x0c302040 = 0x00000075; # gen2_i2c_sda_pdd0: i2c2, pull-down, input-enable

After applying these the SPE GPIO example app works but the jetson-io does not.

Hello, teemu1:
After applying these the SPE GPIO example app works but the jetson-io does not.
That’s expected. It’s better not control one GPIO pin in both SPE R5 and CCPLEX.
Once it’s used by SPE firmware, please do not touch in Linux side, to prevent confliction.

br
ChenJian

Correct, I understand that. But the problem I’m trying to convey here is that after the SPE change the jetson-io tool fails immediately off the bat (when I select the menu option 40pin header). I’ve not even yet tried to do any configuration at this point.

Steps to reproduce.

  1. Apply changes stated in SPE GPIO example app.
  2. Start jetson-io tool
  3. Select option ‘Configure Jetson 40pin header’.

What happens:
I get the error on the screenshot

What I expected.
I can configure available GPIO pins (expect the ones reserved for SPE, those are pins 15 and 27 on the 40pin header).

Hello, teemu1:
Once you make changes as GPIO doc in SPE package mentions, the control is transferred to SPE side. That means all operations/configurations for desired pins should come from SPE side.
So you cannot run tools like jetson-io, in Linux side (CCPLEX) to control the same pin any more.

br
Chenjian

I’m not convinced we’re talking about the same thing now.

Just to confirm: Is it possible to control a different pin? Or does this mean that using a single pin from SPE side will make it impossible to configure anything else with jetson-io? Because where I stand it looks like this is the case.

Hello, teemu1:
Per your statement:

And you changed

tegra194-mb1-bct-scr-cbb-mini-p3668.cfg:
  scr.49.6 = 0x18001010; # GPIO_CC_SCR_04_0

I guess jetson-io may configure all pins in 40pin header, which may include the GPIO CC4.
To clarify the issue, you can configure those pins one by one, through sysfs GPIO nodes.

br
ChenJian

Thank you, this confirms what I suspected. I’ll use the sysfs (or libgpiod)

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