I’m also interested in using the TC358743 chip on the Jetson Nano. I’m currently testing with an Auvidea B101. I am aware of Ridgerun’s services, but for the time being I’d like to understand the drivers myself. Currently I’m having trouble with the clock (or at least I think I do), it looks like it needs at least a 26 MHz clock and so far the most I can supply it with is 24 MHz.
I’ve modified the device tree file from https://devtalk.nvidia.com/default/topic/1011640/jetson-tx2/tc358743-on-tx2/post/5229417/#5229417 to get the right i2c bus on the developer board’s CSI port. I’ve also modified the tc358743 driver to not error out when given a 24 MHz clock, since as far as I know that’s the fastest the CSI clock will go.
Here’s a snippet of the dtsi file I altered, I also changed the clock source from the original.
i2c@546c0000 { /* I2C_PM, "adapter" 6 */
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
tc358743_b@0f {
clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_3>;
clock-names = "clk_out_3";
clock-frequency = <24000000>;
mclk_khz=<24000>;
status = "okay";
compatible = "tc358743";
reg = <0x0f>; /* shifted by 2 */
mclk = "clk_out_3";
reset-gpios = <&gpio 152 0>;
refclk_hz = <24000000>;
/* Physical dimensions of sensor */
physical_w = "4.713";
physical_h = "3.494";
/* Sensor Model */
sensor_model ="tc358743";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tc358743_out0: endpoint {
csi-port = <0>; /* CSI B */
bus-width = <2>; /* Use CSI-B only */
data-lanes = <1 2>;
clock-lanes = <0>;
clock-noncontinuous;
link-frequencies = /bits/ 64 <297000000>;
remote-endpoint = <&tc358743_vi_in0>;
};
};
};
};
};
};
Here’s the output of v4l2-ctl --log-status:
[ 49.619533] vi 54080000.vi: ================= START STATUS =================
[ 49.620308] tc358743 6-000f: -----Chip status-----
[ 49.620562] tc358743 6-000f: Chip ID: 0x00
[ 49.620814] tc358743 6-000f: Chip revision: 0x00
[ 49.620817] tc358743 6-000f: Reset: IR: 0, CEC: 0, CSI TX: 0, HDMI: 0
[ 49.620820] tc358743 6-000f: Sleep mode: on
[ 49.620823] tc358743 6-000f: Cable detected (+5V power): yes
[ 49.621064] tc358743 6-000f: DDC lines enabled: no
[ 49.621295] tc358743 6-000f: Hotplug enabled: no
[ 49.621580] tc358743 6-000f: CEC enabled: no
[ 49.621583] tc358743 6-000f: -----Signal status-----
[ 49.621585] tc358743 6-000f: TMDS signal detected: no
[ 49.621587] tc358743 6-000f: Stable sync signal: no
[ 49.621590] tc358743 6-000f: PHY PLL locked: yes
[ 49.621592] tc358743 6-000f: PHY DE detected: no
[ 49.622028] tc358743 6-000f: No video detected
[ 49.622033] tc358743 6-000f: Configured format: 0x0p0.0 (0x0)
[ 49.622036] tc358743 6-000f: horizontal: fp = 0, -sync = 0, bp = 0
[ 49.622039] tc358743 6-000f: vertical: fp = 0, -sync = 0, bp = 0
[ 49.622041] tc358743 6-000f: pixelclock: 0
[ 49.622044] tc358743 6-000f: flags (0x0):
[ 49.622046] tc358743 6-000f: standards (0x0):
[ 49.622048] tc358743 6-000f: -----CSI-TX status-----
[ 49.622051] tc358743 6-000f: Lanes needed: 0
[ 49.622370] tc358743 6-000f: Lanes in use: 3
[ 49.622626] tc358743 6-000f: Waiting for particular sync signal: yes
[ 49.622881] tc358743 6-000f: Transmit mode: no
[ 49.623136] tc358743 6-000f: Receive mode: yes
[ 49.623392] tc358743 6-000f: Stopped: yes
[ 49.623394] tc358743 6-000f: Color space: Unsupported
[ 49.623625] tc358743 6-000f: -----DVI-D status-----
[ 49.623628] tc358743 6-000f: HDCP encrypted content: no
[ 49.623630] tc358743 6-000f: Input color space: RGB full range
[ 49.623860] vi 54080000.vi: ================== END STATUS ==================
I can see some i2c traffic from the chip, but there’s no other activity other than status checks when I try to play a video. The post from https://devtalk.nvidia.com/default/topic/1011640/jetson-tx2/tc358743-on-tx2/post/5229417/#5229417 mentions declaring the EDID, which I haven’t figured out how to do yet since I don’t know if it’s critical at this point or not. I know the clock is likely an issue.
I’ve seen references to clk_set_parent(refclk, parent) from https://devtalk.nvidia.com/default/topic/1037888/jetson-tx2/cam2_mclk-weird-behaviour/ which I don’t know if that would make it possible to set a faster CSI clock on the Nano, or if I have to wait for a custom carrier board with a proper external clock.