Jetson NANO CSI camera imx334 can't work

Hello,
we use our custom board for nano,use 4 lines csi for imx334.
when we run: ‘v4l2-ctl --set-fmt-video=width=1920,height=1080,pixelformat=NV12 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=2 --stream-to=imx334-2.raw -d /dev/video0’
get error log:
[ 104.024528] imx334 8-001a: probing v4l2 sensor
[ 104.024906] reset-gpio found
[ 104.026740] imx334 8-001a: tegracam sensor driver:imx334_v2.0.6
[ 104.032241] vi 54080000.vi: subdev imx334 8-001a bound
[ 104.033069] imx334 8-001a: Detected IMX334 sensor
[ 104.065916] vi 54080000.vi: Calibrate csi port 4

[ 132.621750] vi 54080000.vi: Calibrate csi port 4
[ 132.627779] vb2-core: __setup_offsets: buffer 0, plane 0 offset 0x00000000
[ 132.631008] vb2-core: __setup_offsets: buffer 1, plane 0 offset 0x003f5000
[ 132.634198] vb2-core: __setup_offsets: buffer 2, plane 0 offset 0x007ea000
[ 132.637373] vb2-core: __setup_offsets: buffer 3, plane 0 offset 0x00bdf000
[ 132.637375] vb2-core: __vb2_queue_alloc: allocated 4 buffers, 1 plane(s) each
[ 132.637635] vb2-core: vb2_mmap: buffer 0, plane 0 successfully mapped
[ 132.637647] vb2-core: vb2_core_qbuf: qbuf of buffer 0 succeeded
[ 132.637925] vb2-core: vb2_mmap: buffer 1, plane 0 successfully mapped
[ 132.637932] vb2-core: vb2_core_qbuf: qbuf of buffer 1 succeeded
[ 132.638194] vb2-core: vb2_mmap: buffer 2, plane 0 successfully mapped
[ 132.638201] vb2-core: vb2_core_qbuf: qbuf of buffer 2 succeeded
[ 132.638458] vb2-core: vb2_mmap: buffer 3, plane 0 successfully mapped
[ 132.638464] vb2-core: vb2_core_qbuf: qbuf of buffer 3 succeeded
[ 132.638598] vb2-core: vb2_core_streamon: successful
[ 132.638626] vb2-core: __vb2_wait_for_done_vb: will sleep waiting for buffers
[ 132.639089] vi 54080000.vi: cil_settingtime was autocalculated
[ 132.639094] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 132.662099] video4linux video0: tegra_channel_capture_frame_single_thread: valid_ports:1 timeout:50
[ 133.085114] video4linux video0: frame start syncpt timeout!0
[ 133.091430] video4linux video0: addr:ffffff800ac00500+132 TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[ 133.091457] vi 54080000.vi: addr:ffffff800ac01838+28 TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 133.091478] vi 54080000.vi: addr:ffffff800ac0192c+16 TEGRA_CSI_CIL_STATUS 0x00000012
[ 133.091497] vi 54080000.vi: addr:ffffff800ac0192c+20 TEGRA_CSI_CILX_STATUS 0x00060061
[ 133.091606] vi 54080000.vi: cil_settingtime was autocalculated
[ 133.091625] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 133.091758] vb2-core: vb2_buffer_done: done processing on buffer 0, state: 4
[ 133.091830] video4linux video0: tegra_channel_capture_frame_single_thread: valid_ports:1 timeout:50
[ 133.501004] video4linux video0: frame start syncpt timeout!0
[ 133.507342] video4linux video0: addr:ffffff800ac00500+132 TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[ 133.507369] vi 54080000.vi: addr:ffffff800ac01838+28 TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 133.507389] vi 54080000.vi: addr:ffffff800ac0192c+16 TEGRA_CSI_CIL_STATUS 0x00000012
[ 133.507407] vi 54080000.vi: addr:ffffff800ac0192c+20 TEGRA_CSI_CILX_STATUS 0x00020060
[ 133.507517] vi 54080000.vi: cil_settingtime was autocalculated
[ 133.507536] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 133.507661] vb2-core: vb2_buffer_done: done processing on buffer 1, state: 4
[ 133.507728] video4linux video0: tegra_channel_capture_frame_single_thread: valid_ports:1 timeout:50
[ 133.916347] video4linux video0: frame start syncpt timeout!0
[ 133.922072] video4linux video0: addr:ffffff800ac00500+132 TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[ 133.922079] vi 54080000.vi: addr:ffffff800ac01838+28 TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 133.922084] vi 54080000.vi: addr:ffffff800ac0192c+16 TEGRA_CSI_CIL_STATUS 0x00000010
[ 133.922088] vi 54080000.vi: addr:ffffff800ac0192c+20 TEGRA_CSI_CILX_STATUS 0x00000040
[ 133.922127] vi 54080000.vi: cil_settingtime was autocalculated
[ 133.922130] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 133.922146] vb2-core: vb2_buffer_done: done processing on buffer 2, state: 4
[ 133.922174] video4linux video0: tegra_channel_capture_frame_single_thread: valid_ports:1 timeout:50
[ 134.332903] video4linux video0: frame start syncpt timeout!0
[ 134.339229] video4linux video0: addr:ffffff800ac00500+132 TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[ 134.339256] vi 54080000.vi: addr:ffffff800ac01838+28 TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 134.339276] vi 54080000.vi: addr:ffffff800ac0192c+16 TEGRA_CSI_CIL_STATUS 0x00000010
[ 134.339295] vi 54080000.vi: addr:ffffff800ac0192c+20 TEGRA_CSI_CILX_STATUS 0x00000040
[ 134.339404] vi 54080000.vi: cil_settingtime was autocalculated
[ 134.339425] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 134.339549] vb2-core: vb2_buffer_done: done processing on buffer 3, state: 4
[ 134.339615] video4linux video0: tegra_channel_capture_frame_single_thread: valid_ports:1 timeout:50
[ 134.748706] video4linux video0: frame start syncpt timeout!0
[ 134.755043] video4linux video0: addr:ffffff800ac00500+132 TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[ 134.755071] vi 54080000.vi: addr:ffffff800ac01838+28 TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 134.755091] vi 54080000.vi: addr:ffffff800ac0192c+16 TEGRA_CSI_CIL_STATUS 0x00000010
[ 134.755110] vi 54080000.vi: addr:ffffff800ac0192c+20 TEGRA_CSI_CILX_STATUS 0x00000040
[ 134.755223] vi 54080000.vi: cil_settingtime was autocalculated
[ 134.755242] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 134.755376] vb2-core: vb2_buffer_done: done processing on buffer 0, state: 4
[ 134.755447] video4linux video0: tegra_channel_capture_frame_single_thread: valid_ports:1 timeout:50
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I can’t find a solution!! anyone help me?

thanks

From the TRM the TEGRA_CSI_CILX_STATUS 0x00020060,
Try modify the discontinuous_clk = “yes” to try, if still not any improve you may need to check the output signal is follow the MIPI spec.

CILA_DATA_LANE0_CTRL_ERR: Control Error. Set when CIL-A detects LP state 01 or 10 followed by a
stop state (LP11) instead of transitioning
5 X CILA_DATA_LANE0_SOT_MB_ERR: Start of Transmission Multi Bit Error. Set when CIL-A detects a multi
bit start of transmission byte error in one of the packet’s SOT bytes on data lane-0. The packet will be