From the TRM the TEGRA_CSI_CILX_STATUS 0x00020060,
Try modify the discontinuous_clk = “yes” to try, if still not any improve you may need to check the output signal is follow the MIPI spec.
CILA_DATA_LANE0_CTRL_ERR: Control Error. Set when CIL-A detects LP state 01 or 10 followed by a
stop state (LP11) instead of transitioning
5 X CILA_DATA_LANE0_SOT_MB_ERR: Start of Transmission Multi Bit Error. Set when CIL-A detects a multi
bit start of transmission byte error in one of the packet’s SOT bytes on data lane-0. The packet will be