cospan
#1
Within the Jetson Xavier Nano Product Design Guide V0.9 Page 18
Pinout diagram:
PCIE1_CLKREQ and PCIE0_CLKREQ are the same pin
PCIE1_RST and PCIE0_RST are the same pin
Looking at the schematic for the Jetson Nano Carrier Board it seems as though the following pins are correct
PCIE0_CLKREQ: pin 180
PCIE0_RST: pin 181
PCIE1_CLKREQ: pin 182
PCIE1_RST: pin 183
Can I get a confirmation.
Thanks,
Dave
cospan
#2
Also on that same diagram:
2 more notes:
PCIE0_TX3_N and PCIE0_TX3_P the numbers are flipped, looking at the Xavier Nano Datasheet as well as the Jetson Nano Reference Design Schematic
PCIE0_TX3_N should be pin 154
PCIE0_TX3_P should be pin 156
PCIE0_RX0_N and PCIE0_RX0_P numbers are incorrect:
PCIE0_RX0_N should be pin 131
PCIE0_RX0_P should be pin 133
Can I get a confirmation on this,
Thanks,
Dave
cospan
#3
Page 12 Figure 4-1:
USB2_D_P and USB2_D_N: are flipped
USB2_D_P should be pin 123
USB2_D_N should be pin 121
Trumany
#4
Hi, thanks for your findings, we will check that and will update the docs if necessary, thanks.